 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| DATA SHEET MICRONAS CDC 32xxG-C Automotive Controller Family User Manual CDC 3205G-C Automotive Controller Specification Edition Feb. 10, 2005 6251-579-1DS MICRONAS CDC 32xxG-C Contents Page 7 7 10 11 13 13 16 17 17 21 22 25 25 26 27 37 39 39 39 43 46 47 48 50 53 54 55 56 59 59 60 61 62 64 68 71 72 73 77 79 80 81 Section 1. 1.1. 1.2. 1.3. 2. 2.1. 2.2. 2.3. 2.4. 2.5. 2.6. 3. 3.1. 3.2. 3.3. 3.4. 4. 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.7. 5. 5.1. 5.2. 5.3. 6. 6.1. 6.2. 6.3. 6.4. 6.5. 6.6. 7. 7.1. 7.2. 7.3. 7.4. 7.5. 7.6. Title Introduction Features Abbreviations Block Diagram Packages and Pins Pin Assignment Package Outline Dimensions Multiple-Function Pins Pin Function Description External Components Pin Circuits Electrical Data Absolute Maximum Ratings Recommended Operating Conditions Characteristics Recommended Quartz Crystal Characteristics CPU and Clock System ARM7TDMITM CPU Operating Modes Clock System Memory Controller EMI Reduction Module (ERM) Registers PLL/ERM Application Notes Memory and Special Function ROM (SFR) System RAM and ROM I/O Map Special Function ROM (SFR) Core Logic Control Word (CW) Device Lock Module (DLM) Standby Registers UVDD Analog Section Reset Logic Test Registers Power Saving Module (PSM) Functional Description Registers Operation of Power Saving Module Operation of RTC Module Operation of Polling Module Operation of Port Wake Module DATA SHEET 2 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Contents, continued Page 83 83 84 84 84 87 87 89 89 90 91 91 94 94 96 96 99 99 99 100 101 103 103 105 107 109 110 111 112 112 112 112 113 113 115 117 117 119 Section 8. 8.1. 8.2. 8.3. 8.4. 9. 9.1. 10. 10.1. 10.2. 11. 11.1. 11.2. 11.3. 11.4. 11.5. 12. 12.1. 12.2. 12.3. 13. 14. 14.1. 14.2. 14.3. 14.4. 14.5. 15. 15.1. 15.2. 15.3. 15.4. 15.5. 15.6. 15.7. 16. 16.1. 16.2. Title JTAG Interface Functional Description Registers External Circuit Layout JTAG ID Embedded Trace Module (ETM) Functional Description Memory Patch Module V1.0 Principle of Operation Registers IRQ Interrupt Controller Unit (ICU) Functional Description Timing Registers Principle of Operation Application Hints FIQ Interrupt Logic Functional Description Registers Principle of Operation Port Interrupts Ports Analog Input Port Universal Ports U0 to U8 Universal Port Registers High Current Ports H0 to H7 High Current Port Registers AVDD Analog Section VREFINT Generator BVDD Regulator Wait Comparator P0.6 Comparator PLL/ERM A/D Converter (ADC) Registers Timers (TIMER) Timer T0 Timer T1 to T4 Micronas Feb. 10, 2005; 6251-579-1DS 3 CDC 32xxG-C Contents, continued Page 121 121 122 125 125 126 127 129 131 133 133 135 135 136 139 139 142 142 143 143 145 146 147 151 151 151 152 155 156 157 158 159 160 162 164 167 168 170 Section 17. 17.1. 17.2. 18. 18.1. 18.2. 19. 19.1. 19.2. 20. 20.1. 20.2. 20.3. 20.4. 21. 21.1. 21.2. 21.3. 22. 22.1. 22.2. 22.3. 22.4. 23. 23.1. 23.2. 23.3. 24. 24.1. 24.2. 24.3. 25. 25.1. 25.2. 25.3. 26. 26.1. 26.2. Title Pulse Width Modulator (PWM) Principle of Operation Registers Pulse Frequency Modulator (PFM) Principle of Operation Registers Capture Compare Module (CAPCOM) Principle of Operation Registers Stepper Motor Module (SMM) Functional Description Registers Principle of Operation Rotor Zero Position Detection (RZPD) LCD Module Principle of Operation Registers Application Hints for Cascading LCD Modules DMA Controller Functions Registers Principle of Operation Timing Diagrams Graphic Bus Interface Functions GB Registers Principle of Operation Serial Synchronous Peripheral Interface (SPI) Principle of Operation Registers Timing Universal Asynchronous Receiver Transmitter (UART) Principle of Operation Timing Registers I2C-Bus Master Interface Principle of Operation Registers DATA SHEET 4 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Contents, continued Page 173 174 174 180 186 187 189 189 189 190 191 193 193 194 196 199 202 203 204 208 209 209 209 210 215 215 221 223 249 249 252 253 261 262 Section 27. 27.1. 27.2. 27.3. 27.4. 27.5. 28. 28.1. 28.2. 28.3. 28.4. 29. 29.1. 29.2. 29.3. 29.4. 29.5. 30. 30.1. 30.2. 31. 31.1. 31.2. 31.3. 32. 32.1. 32.2. 33. 34. 34.1. 34.2. 34.3. 35. 36. Title CAN Manual Abbreviations Functional Description Application Notes Bit Timing Logic Bus Coupling DIGITbus System Description Bus Signal and Protocol Other Features Standard Functions Optional Functions DIGITbus Master Module Context Functional Description Registers Principle of Operation Timings Audio Module (AM) Functional Description Registers Hardware Options Functional Description Listing of Dedicated Addresses of the Hardware Options Field HW Options Registers and Code Register Cross Reference Table 8-Bit I/O Region 32-Bit I/O Region Register Quick Reference Control Register and Memory Interface Control Register CR Memory Clock Delay Lines External Memory Interface Differences Data Sheet History Micronas Feb. 10, 2005; 6251-579-1DS 5 CDC 32xxG-C Contents, continued Page Section Title DATA SHEET 6 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 1. Introduction Release Note: Revision bars changes to the previous edition. indicate significant The chip contains timer/counters, interrupt controller, multichannel AD converter, stepper motor and LCD driver, CAN interfaces and PWM outputs and a crystal clock multiplying PLL. The device is a microcontroller for use in automotive applications. The on-chip CPU is an ARM processor ARM7TDMI with 32-bit data and address bus, which supports Thumb format instructions. 1.1. Features Table 1-1: CDC32xxG-C Family Feature List This Device: Item CDC3205GC MCM Flash CDC3207GC MCM Flash CDC3217GC MCM Flash CDC3257GC2 MCM Flash CDC3272GC Mask ROM CDC3231GC Mask ROM Core CPU CPU-active operation modes Power-saving operation modes (CPU inactive) CPU clock multiplication EMI reduction mode Oscillators RAM, zero wait state, 32 bit wide ROM 32-bit ARM7TDMI DEEP SLOW, SLOW, FAST and PLL IDLE, WAKE and STANDBY PLL delivering up to 50 MHz selectable in PLL mode 4 to 5 MHz quartz and 32 kHz internal RC 32 Kbyte ROMless, ext. up to 4 M x 32/ 8 M x 16 512-Kbyte Flash (256 K x 16) top-boot conf. 1024-Kbyte Flash (512 K x 16) top-boot conf. 12 Kbyte 256-Kbyte Flash (128 K x 16) top-boot conf. 16 Kbyte 384 Kbyte (96 K x 32/ 192 K x 16) 6 Kbyte 128 Kbyte (32 K x 32/ 64 K x 16) Boot ROM Digital watchdog Central clock divider Interrupt controller expanding IRQ Port interrupts including slope selection Port wake-up inputs including slope/level selection Patch module 8 Kbyte (special function ROM) 40 inputs, 16 priority levels 26 inputs, 16 priority levels 5 inputs 6 inputs 10 inputs 10 ROM locations Micronas Feb. 10, 2005; 6251-579-1DS 7 CDC 32xxG-C Table 1-1: CDC32xxG-C Family Feature List This Device: Item CDC3205GC MCM Flash CDC3207GC MCM Flash CDC3217GC MCM Flash CDC3257GC2 MCM Flash CDC3272GC Mask ROM - DATA SHEET CDC3231GC Mask ROM Boot system Device lock module Analog Reset/Alarm Clock and supply supervision 10-bit ADC, charge balance type ADC reference Comparators LCD Communication DMA UART Synchronous serial peripheral interfaces Full CAN modules V2.0B each with a 32-object RAM (LCAN000E) DIGITbus I2C Graphics bus interface Input & Output Universal ports selectable as 4:1-mux LCD segment/backplane lines or digital I/O ports allows in-system downloading of external code to Flash memory via JTAG inhibits access to internal firmware, lock can be set by customer combined input for regulator input supervision 16 channels (each selectable as digital input) VREF pin, P1.0 pin, P1.1 pin or VREFINT internal bandgap selectable P06COMP with 1/2 AVDD reference, WAITCOMP with internal bandgap reference internal processing of all analog voltages for the LCD driver 3 DMA channels, one each for serving the graphics bus interface, SPI0 and SPI1 2: UART0 and UART1 2: SPI0 and SPI1, DMA supported 4: CAN0, CAN1, CAN2 and CAN3 2: CAN0 and CAN1 UART0 1: CAN0 1 master module 2 master modules: I2C0 and I2C1 8-bit data bus, DMA supported, e.g., for connection of EPSON SED 1560 LCD controller I2C0 - up to 52 I/O or 48 LCD segment lines (= 192 segments), individually configurable as I/O or LCD up to 50 I/O or 46 LCD segment lines (= 184 segments) Universal port slew rate Stepper motor control modules with high-current ports SW-selectable 7 modules, 32 dI/dt-controlled ports 4 modules 23 dI/dtcontrolled ports 8 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Table 1-1: CDC32xxG-C Family Feature List This Device: Item CDC3205GC MCM Flash CDC3207GC MCM Flash CDC3217GC MCM Flash CDC3257GC2 MCM Flash CDC3272GC Mask ROM CDC3231GC Mask ROM 5 modules: PWM0/1, PWM2/3, PWM4/5, PWM6/7, PWM8/9 - PWM modules, each configurable as two 8-bit PWMs or one 16-bit PWM 6 modules: PWM0/1, PWM2/3, PWM4/5, PWM6/7, PWM8/9 and PWM10/ 11 Pulse/frequency modulator Audio module with auto-decay SW-selectable clock outputs Polling/flash timer output Timers & Counters 16-bit free-running counters with capture/compare modules 16-bit timers 8-bit timers Real-time clock, delivering hours, minutes and seconds Miscellaneous Scalable layout in CAN, RAM and ROM Various HW options selectable at random JTAG interface On-chip debug aids 2: PFM0 and PFM1 2 1 high-current port output operable in power-saving operation modes CCC0 with 4 CAPCOM CCC1 with 2 CAPCOM 1: T0 4: T1, T2, T3 and T4 CCC0 with 4 CAPCOM - set by copy from user program storage during system start-up allows Flash programming Embedded trace module, JTAG JTAG Core bond-out Supply voltage Case temperature range Package Type Bonded pins - 3.5 to 5.5 V (limited I/O performance below 4.5 V) 0 C to +70 C -40 C to +105 C ceramic 257PGA 256 plastic 128QFP 0.5 mm pitch 128 128 128 126 111 ARM and Thumb are the registered trademarks of ARM Limited. ARM7TDMI is the trademark of ARM Limited. Micronas Feb. 10, 2005; 6251-579-1DS 9 CDC 32xxG-C 1.2. Abbreviations ADC AM CAN CAPCOM CCC CPU DMA ERM ETM I2C LCD P06COMP PWM SM SPI T UART WAITCOMP Analog-to-Digital Converter Audio Module Controller Area Network Module Capture/Compare Module Capture/Compare Counter Central Processing Unit Direct Memory Access Module EMI Reduction Mode Embedded Trace Module I2C Interface Module Liquid Crystal Display Module P0.6 Alarm Comparator Pulse Width Modulator Module Stepper Motor Control Module Serial Synchronous Peripheral Interface Timer Universal Asynchronous Receiver Transmitter Wait Comparator DATA SHEET 10 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 1.3. Block Diagram FVDD FVSS EVDD EVSS 52 21 WAIT WAITH VREFINT VREF AVDD AVSS BVDD 8 PPort0 ARM7TDMI CPU 2.5 V Reg. Data, Address, Control 3.3 V Reg. UVDD UVSS 2.5 V Reg. VDD VSS Reset/Alarm Test Watchdog Clock PLL/ERM RESETQ TEST TEST2 XTAL1 XTAL2 ETM 40-Input Interrupt Controller RC Oscillator RTC Power Saving SRAM 8K x 32 DMA Logic Bridge 32 Wait Comp. P06 Comp. Memory Controller 16 JTAG Test and Debug Interface 5 PPort1 8 2 PPort2 Special Function ROM 4K x 16 Patch 10 Locations UPort0 8 UPort1 8 HPort0 4 Bandgap Ref. 10-bit ADC Bridge 8 UPort3 Device Lock Module UPort2 7 4 HPort2 HPort1 4 UART 0 UART 1 LCD Control Audio Module Stepper Motor Control 8-bit PWM 0 8/16-bit PWM 1 16-bit Timer 0 8-bit Timer 1 8-bit Timer 2 8-bit Timer 3 8-bit Timer 4 16-bit CCC 0 CAPCOM 0 CAPCOM 1 CAPCOM 2 8 HPort3 4 SPI 0 SPI 1 CAN 0 CAN 1 CAN 2 CAN 3 DIGITbus Clock Out 0 UPort4 4 HPort4 8-bit PWM 2 CAPCOM 3 16-bit CCC 1 CAPCOM 4 UPort6 CAPCOM 5 3 UPort5 4 4 Clock Out 1 Phase/Freq. Modulator 0 Phase/Freq. Modulator 1 8/16-bit PWM 3 8-bit PWM 4 8/16-bit PWM 5 8-bit PWM 6 8/16-bit PWM 7 8-bit PWM 8 8/16-bit PWM 9 8-bit PWM 10 4 4 HPort7 HPort6 HPort5 4 I2 C UPort7 0 4 HVDD0 HVSS0 HVDD1 HVSS1 HVDD2 HVSS2 HVDD3 HVSS3 I2 C 1 Graphics Bus UPort8 8/16-bit PWM 11 6 UVDD1 UVSS1 Fig. 1-1: CDC3205G-C block diagram Micronas Feb. 10, 2005; 6251-579-1DS 11 CDC 32xxG-C DATA SHEET 12 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 2. Packages and Pins 2.1. Pin Assignment 20 Y W V U T R P N M L K J H G F E D C B A 19 18 17 16 15 14 13 12 11 97 10 95 96 9 93 90 86 88 8 91 87 84 82 7 89 83 80 78 6 85 79 76 74 5 81 75 72 70 4 77 71 68 66 62 58 54 48 42 36 3 73 67 64 60 56 52 50 46 44 38 28 22 20 16 12 8 4 2 69 63 59 55 51 47 43 39 40 34 32 26 23 19 15 11 7 3 1 65 61 57 53 49 45 41 37 35 33 31 29 27 25 21 17 13 9 5 1 1 Y W V U T R P N M L K J H G F E D C B A 129 125 121 117 113 109 105 101 99 133 127 123 119 115 111 107 103 104 98 137 131 128 124 120 116 114 110 108 102 92 141 135 132 130 126 122 118 112 106 100 94 145 139 136 134 149 143 140 138 153 147 144 142 155 151 148 146 157 154 150 152 159 160 156 158 Top View 161 162 166 164 163 168 172 170 165 167 174 176 169 171 178 182 173 175 180 186 177 179 184 190 257 30 24 18 14 10 6 2 181 183 188 194 198 202 206 210 216 222 228 234 240 246 250 254 185 187 192 196 200 204 208 212 214 220 230 236 238 242 244 248 252 256 189 191 195 199 203 207 211 215 218 224 226 232 231 235 239 243 247 251 255 193 197 201 205 209 213 217 219 221 223 225 227 229 233 237 241 245 249 253 20 19 18 17 16 15 14 13 12 11 10 65 129 9 8 7 6 5 4 3 2 Top View 193 257 1 A1 Fig. 2-1: Pin map of CPGA257 package Micronas Feb. 10, 2005; 6251-579-1DS 13 CDC 32xxG-C Table 2-1: Pin assignment for CPGA257 package PQFP128 Pin No. CPGA257 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Coord. A1 D4 C2 D3 B1 E4 D2 E3 C1 F4 E2 F3 D1 G4 F2 G3 E1 H4 G2 H3 F1 J3 H2 J4 G1 J2 H1 K3 J1 K4 K1 K2 L1 L2 M1 L4 N1 L3 N2 M2 P1 M4 P2 M3 R1 N3 R2 N4 T1 P3 T2 R3 U1 P4 U2 T3 V1 R4 V2 U3 W1 T4 W2 V3 Pin Functions Basic Function U5.3/GD3 U5.2/GD2 U5.1/GD1 U5.0/GD0 U2.1 U2.0 U1.7 U1.6 U1.5 TEST RESETQ/ALARMQ XTAL2 XTAL1 VSS VDD U1.4 U1.3 U1.2 U1.1 U1.0 U0.7 U0.6 U0.5 U0.4 U0.3 U0.2 U0.1 U0.0 D31 D30 D29 D28 D27 D26 D25 EVDD8 EVSS8 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D7 D14 EVDD7 EVSS7 D6 D13 D5 D12 D4 D11 D3 D10 D2 D9 D1 D8 EVDD6 WP4 CC3-IN PINT4 PINT5 WP3 MTI/ITSTIN ITSTOUT/AM-OUT MTO/AM-PWM T0-OUT/INTRES T1-OUT T2-OUT T3-OUT T4-OUT/CC3-OUT CC3-OUT CO1 PWM0 PWM1 PWM2 PWM3 SEG1.4 SEG1.3 SEG1.2 SEG1.1 SEG1.0 SEG0.7 SEG0.6 SEG0.5 SEG0.4 SEG0.3 SEG0.2 SEG0.1 SEG0.0 SDA0/CAN0-RX/WP6 SCL0 PINT0/WP0 PINT1 PINT2 Port Special In CC4-IN SDA1 SCL1 Port Special Out CC4-OUT SDA1 SCL1 PFM0 SDA0 SCL0/CAN0-TX PFM0 CO0/INTRES CO0Q/CO1 LCD Mode SEG5.3 SEG5.2 SEG5.1 SEG5.0 SEG2.1 SEG2.0 SEG1.7 SEG1.6 SEG1.5 DATA SHEET Table 2-1: Pin assignment for CPGA257 package Pin No. 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Coord. Y1 U4 W3 V4 Y2 U5 W4 V5 Y3 U6 W5 V6 Y4 U7 W6 V7 Y5 U8 W7 V8 Y6 V9 W8 U9 Y7 W9 Y8 V10 Y9 U10 Y10 W10 Y11 W11 Y12 U11 Y13 V11 W13 W12 Y14 U12 W14 V12 Y15 V13 W15 U13 Y16 V14 W16 V15 Y17 U14 W17 V16 Y18 U15 W18 V17 Y19 U16 W19 V18 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 PQFP128 Pin No. CPGA257 Pin Functions Basic Function EVSS6 D0 OEQ CE0Q BWQ3 BWQ2 BWQ1 BWQ0 EMUTRI ABORT EXTERN0 EXTERN1 H7.3 H7.2 H7.1 H7.0 HVDD2 HVSS2 H6.3 H6.2 H6.1 H6.0 H5.3 H5.2 HVDD0 HVSS0 H5.1 H5.0 H4.3 H4.2 H4.1 H4.0 H3.3 H3.2 H3.1 H3.0 H2.3 H2.2 HVDD1 HVSS1 H2.1 H2.0 H1.3 H1.2 H1.1 H1.0 HVDD3 HVSS3 H0.3 H0.2 H0.1 H0.0 nTRST ETDI ETMS ETCK ETDO ABE CE1Q FBUSQ AMCS1 AICU2 AICU3 EVSS5 SMG-COMP3 SMG-COMP2 SMG-COMP1 SMG-COMP0 SMG1+/PWM1 SMG1-/PWM3/POL SMG2+/PWM5 SMG2-/PWM7 SMC-COMP1 SMC-COMP0 SMF-COMP3 SMF-COMP2 SMF-COMP1 SMF-COMP0 SMC2+ SMC2SMF1+ SMF1SMF2+ SMF2SMD-COMP1 SMD-COMP0 SMA-COMP3 SMA-COMP2 SMA-COMP1 SMA-COMP0 SMB-COMP3 SMB-COMP2 SMB-COMP1 SMB-COMP0 SMC-COMP3 SMC-COMP2 SMD2+ SMD2SMA1+ SMA1SMA2+ SMA2SMB1+ SMB1SMB2+ SMB2SMC1+ SMC1SMD-COMP3 SMD-COMP2 PWM8 PWM9 PWM10 PWM11 SMD1+ SMD1SME-COMP3 SME-COMP2 SME-COMP1 SME-COMP0 SME1+/PWM4 SME1-/PWM6 SME2+/PWM8 SME2-/PWM9 Port Special In Port Special Out LCD Mode 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 14 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Table 2-1: Pin assignment for CPGA257 package LCD Mode Pin No. 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 PINT5 PINT4 PINT3 PINT2 PINT1 PINT0 VREF1/WP2 VREF0/WP1 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 P06COMP 245 246 247 248 249 250 CC4-IN 251 252 253 GWEQ CAN1-RX/WP7 GOEQ CAN1-TX SEG6.2 SEG6.1 SEG6.0 254 255 256 257 Coord. A20 D17 B18 C17 A19 D16 B17 C16 A18 D15 B16 C15 A17 D14 B15 C14 A16 D13 B14 C13 A15 C12 B13 D12 A14 B12 A13 C11 A12 D11 A11 B11 A10 B10 A9 D10 A8 C10 B8 B9 A7 D9 B7 C9 A6 C8 B6 D8 A5 C7 B5 C6 A4 D7 B4 C5 A3 D6 B3 C4 A2 D5 B2 C3 E5 PQFP128 Pin No. CPGA257 Pin Functions Basic Function Port Special In CAN2-RX/PINT3/WP8 LCD-SYNC-IN CAN3-RX/WP9 LCD-CLK-IN Port Special Out LCD-SYNC-OUT CAN2-TX LCD-CLK-OUT CAN3-TX CC3-OUT CC4-OUT CAN0-RX/WP5 CC0-IN SPI1-D-IN SPI1-CLK-IN SPI0-D-IN SPI0-CLK-IN CC0-IN / TCK CC1-IN / TMS CC2-IN / TDI TO2 CAN0-TX SPI1-D-OUT CC0-OUT SPI1-CLK-OUT SPI0-D-OUT TO3 SPI0-CLK-OUT CO0/TDO CC0-OUT CC1-OUT CC2-OUT LCD Mode SEG8.5 SEG8.4 SEG8.3 SEG8.2 SEG8.1 SEG8.0 BP3 BP2 BP1 BP0 SEG3.7 SEG3.6 SEG3.5 SEG3.4 SEG3.3 SEG3.2 SEG3.1 SEG3.0 Table 2-1: Pin assignment for CPGA257 package Pin No. 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 Coord. Y20 U17 V19 U18 W20 T17 U19 T18 V20 R17 T19 R18 U20 P17 R19 P18 T20 N17 P19 N18 R20 M18 N19 M17 P20 M19 N20 L18 M20 L17 L20 L19 K20 K19 J20 K17 H20 K18 H19 J19 G20 J17 G19 J18 F20 H18 F19 H17 E20 G18 E19 F18 D20 G17 D19 E18 C20 F17 C19 D18 B20 E17 B19 C18 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 PQFP128 Pin No. CPGA257 Pin Functions Basic Function EVDD5 AICU4 AICU5 AICU6 AICU7 A8 A18 A19 EVDD4 EVSS4 WEQ/RWQ A9 A10 A11 A12 A13 A14 A15 EVDD3 EVSS3 A16 A17 A20 A21 A22 A23 AMCM21 AMCM22 EVDD2 EVSS2 AMCM23 SEQ nMREQ MAS0 MAS1 nRESET P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 VREF VREFINT AVDD AVSS BVDD WAIT WAITH P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 P2.1 P2.0 U6.2 U6.1 U6.0 Port Special In Port Special Out 100 U8.5 101 U8.4 102 U8.3 103 U8.2 104 U8.1 105 U8.0 106 U4.3 107 U4.2 108 U4.1 109 U4.0 110 U3.7 111 U3.6 112 U3.5 113 U3.4 114 U3.3 115 U3.2 116 U3.1 117 U3.0 118 TEST2 119 UVDD1 120 UVSS1 TRACEPKT0 / TBIT TRACEPKT1 / nM0 TRACEPKT2 / nM1 TRACEPKT3 / nM2 TRACEPKT4 / nM3 TRACEPKT5 / nM4 EVDD1 EVSS1 TRACEPKT6 / LOCK TRACEPKT7 / nEXEC TRACEPKT8 / nOPC TRACEPKT9 / nTRANS TRACEPKT10 / A5 TRACEPKT11 / A6 TRACEPKT12 / RANGEOUT0 TRACEPKT13 / RANGEOUT1 TRACEPKT14 / A7 TRACEPKT15 / BREAKPT PIPESTAT0 / nRW PIPESTAT1 / A0 PIPESTAT2 / A1 EVDD0 EVSS0 TRACESYNC/A2 TRACECLK/A3 EXTTRIG/A4 FSYS nWAIT DBGACK DBGRQ UVDD UVSS 121 U2.6 122 U2.5 123 U2.4 124 U2.3 125 U2.2 126 U7.7/GD7 127 U7.6/GD6 128 U7.5/GD5 1 2 3 U7.4/GD4 FVDD FVSS Extra insertion Pin: connect to system ground CC5-IN DIGIT-IN UART0-RX CC1-IN/DIGIT-IN UART1-RX CC2-IN DIGIT-OUT CC1-OUT UART0-TX CC2-OUT UART1-TX CO0 CO1 LCK/PFM1 CC5-OUT SEG2.6 SEG2.5 SEG2.4 SEG2.3 SEG2.2 SEG7.7 SEG7.6 SEG7.5 SEG7.4 Micronas Feb. 10, 2005; 6251-579-1DS 15 T R P N M L K J H G EXTRA PIN 2.540 0.15 0.8 0.46 0.05 0.2 1 0.1 Fig. 2-2: CPGA257 ceramic pin grid array 257-pin (weight approx. 32 g. Dimensions in mm) Feb. 10, 2005; 6251-579-1DS F E D C B A 0.2 1 0.1 4.80 0.20 1 2 3 4 5 6 7 8 9 INDEX MARK PLATING OPTION 10 11 12 13 14 15 16 17 18 19 20 D0029/1E 2.540 x 19 = 48.26 0.2 16 2.1 0.20 2.540 x 19 = 48.26 0.2 2.540 0.15 0.4 0.1 Y W V U CDC 32xxG-C 2.2. Package Outline Dimensions 50.8 0.5 20.7 0.1 18.85 0.1 DATA SHEET Micronas DATA SHEET CDC 32xxG-C 2.3. Multiple-Function Pins 2.3.1. U-Ports Apart from their basic function (digital I/O), universal ports (with prefix "U") have overlaid alternative functions (see Table 2-1 on page 14). How to enable basic function, special in and special out mode is explained in the functional description of the U-ports. How to enable LCD mode is explained in the functional descriptions of LCD module and U-ports. 2.3.3. Emulator Bus In contrast to the PQFP128 standard package, the CPGA257 package has additional pins (emulator bus) which serve as memory interface, emulation JTAG interface or connection to an external emulation or trace hardware (trace bus). The functionality of the memory interface and the trace bus is controlled by register CR. Refer to section "Control Word" for more information. Some of the following pins are marked as being ARM or ETM signals. For details of the functionality please refer to ARM7TDMI data sheet (document number: ARM DDI 0029) or "Embedded Trace Macro Cell" (document number: ARM IHI 0014 and ARM DDI 0158). 2.3.2. H-Ports Apart from their basic function (digital I/O), high current ports (prefix "H") have overlaid alternative functions (see Table 2-1 on page 14). How to enable basic function, special in and special out mode is explained in the functional description of the H-ports. 2.4. Pin Function Description A0 to A7 (ARM) 1) A8 to A23 (ARM) 4) These 24 lines are the original CPU addresses. Some are used for external memory access on the emulator bus. The function is controlled by register CR. ABE (ARM) 1) 2) This pin outputs the "address bus enable" signal of the ARM. It indicates that the CPU does not access the data and address bus when low. It is not possible to influence the CPU via this pin. ABORT (ARM) 3) This is an input which allows the memory system to tell the processor that a requested access is not allowed. AICU2 to AICU7 4) These pins correspond to the ARM address bus lines A2 to A7, but can be modified by the ICU. In the latter case, AICUx and Ax are not equal. ALARMQ This is the second input comparator level on the RESETQ pin. AMCM21 to AMCM23 4) These pins correspond to the ARM address bus lines A21 to A23 but can be modified by the memory controller. In the latter case, AMCMx and Ax are not equal. AMCS1 4) This pin corresponds to the ARM address bus line A1, but can be modified by the memory controller. In the latter case, AMCS1 and A1 are not equal. AM-OUT This is the output signal of the audio module. AM-PWM This is the output signal of the 8-bit PWM of the audio module. It is intended for testing only. AVDD This is the positive power supply for ADC, P06COMP, WAITCOMP and BVDD regulator. AVDD should be kept at UVDD 0.5 V. It must be buffered by an external capacitor to analog ground AVSS This is the negative reference for the ADC and the negative power supply for ADC, P06COMP, WAITCOMP and PLL. Connect to analog ground. BP0 to BP3 These pin functions serve as backplane drivers for a 4:1 multiplexed LCD. BREAKPT (ARM) 3) This is the input pin for the ARM BREAKPT signal in "full trace" mode. It allows external hardware to halt the execution of the processor for debugging purposes. BVDD This is the output of the internal 2.5 V regulator for the PLL. It must be buffered by an external capacitor to analog ground. BWQ0 to BWQ3 4) This is the byte write control signal to an external 32-bit memory. CAN0-RX, CAN1-RX, CAN2-RX, CAN3-RX These signals provide the input lines for the CAN0, CAN1, CAN2 and CAN3 modules. CAN0-TX, CAN1-TX, CAN2-TX, CAN3-TX These signals provide the output lines for the CAN0, CAN1, CAN2 and CAN3 modules. CC0-IN, CC1-IN, CC2-IN, CC3-IN, CC4-IN, CC5-IN These signals are the capture inputs of the CAPCOM0 to CAPCOM5 modules. Micronas Feb. 10, 2005; 6251-579-1DS 17 CDC 32xxG-C CC0-OUT, CC1-OUT, CC2-OUT, CC3-OUT, CC4-OUT, CC5-OUT These signals are the compare outputs of the CAPCOM0 to CAPCOM5 modules. CE0Q 4) The "Chip Enable" output signal connects to external program memory's CEQ pin. With CR.EFLA set, it serves to reduce program memory's power consumption when CPU operates in slow mode. Active LOW. CE1Q 4) The "chip enable" output signal connects to external RAM or Boot ROM memory's CEQ pin and reduces its power consumption when CPU operates in slow mode. Active LOW. CO0, CO0Q, CO1 These signals provide frequency outputs. They are connected to internal prescaler and multiplexer. They can be hardwired by HW Option. Refer to section "Hardware Options" for setting the CO0/CO1 options and section "CPU and Clock System" setting the "clock out 0" selection register. For testing purposes, it is possible to drive clocks and other signals of internal peripheral modules out of CO0 and CO1. Selection is done via register TST2. D0 to D31 (ARM) 4) These 32 signals are the original CPU bidirectional data bus lines. They provide the 32-bit data bus for use during data exchanges between the microprocessor and external memory or peripherals. DBGACK (ARM) This is the debug acknowledge output signal of the ARM. A high state indicates that ARM is in debug state. DBGRQ (ARM) 3) This is the "debug request input" of the ARM. It is a levelsensitive input, which when high causes ARM to enter debug state after executing the current instruction. DIGIT-IN This is the receive input line of the DIGITbus module. DIGIT-OUT This is the transmit output line of the DIGITbus module. EMUTRI This input signal allows to tristate (= high) the interface pins to external memory (A8 to A23, AMCS1, AICU2 to AICU7, AMCM21 to AMCM23, CE1Q, FBUSQ and WEQ/RWQ). ETCK (ARM) This pin is the ARM "test clock input" (TCK) of the emulation JTAG interface. ETDI (ARM) This pin is the ARM "test data input" (TDI) of the emulation JTAG interface. ETDO (ARM) This pin is the ARM "test data output" (TDO) of the emulation JTAG interface. ETMS (ARM) This pin is the ARM "test mode select" (TMS) input of the emulation JTAG interface. EVDD0 to EVDD8 These nine lines form the positive power supply of the emulator and trace bus drivers. EVDD0 to EVDD8 may be connected to any voltage between 3 to 5.5 V. Normally they are connected to FVDD. DATA SHEET EVSS0 to EVSS8 These nine lines form the negative supply of the emulator bus and trace drivers. EVSS0 to EVSS8 have to be hardwired to system ground. EXTERN0, EXTERN1 (ARM) 3) These are inputs to the ICEBreaker logic of the ARM which allows breakpoints and/or watch points to be dependent on an external condition. EXTTRIG (ETM) 2) This is a trigger input to the ETM. FBUSQ 4) This signal is the reference for access to external synchronous memory. It is active for memory access only. FSYS This signal provides the system frequency clock fSYS. It is the PLL output frequency if PLL is enabled. FVDD This is the output of the internal 3.3 V regulator for the external Flash chip. It must be buffered by an external capacitor to FVSS. FVSS This is the ground reference of the internal 3.3 V regulator for the external Flash chip. GD0 to GD7 These eight graphics IC data lines provide an 8-bit DMAcontrolled data link to an external IC. GOEQ This graphics IC read line provides the control signal for read accesses via the GD7 to GD0 bus. Active LOW. GWEQ This graphics IC write line provides the control signal for write accesses via the GD7 to GD0 bus. Active LOW. H0.0 to H7.3 The high current ports are intended for use as digital I/O which can drive higher currents than the universal ports. HVDD0 to HVDD3 The pins HVDD0 to HVDD3 are the positive power supply of the high current ports H0.0 to H7.3. HVDD0 to HVDD3 should be kept at UVDD 0.5 V. Be careful to design the PCB traces for carrying the considerable operating current on these pins. HVSS0 to HVSS3 The pins HVSS1 to HVSS3 are the negative power supply for the high-current ports H0.0 to H7.3. HVSS0 to HVSS3 have to be hardwired to system ground. Be careful to layout sufficient PCB traces for carrying the considerable operating current on these pins. INTRES Test output of internal reset signal. Only for testing and available only in test mode. ITSTIN Test input signal for interrupt controller. Only for testing and available only in test mode. ITSTOUT Test output signal of internal peripheral modules. Only for testing and available only in test mode. LCD-CLK-IN The clock input of the LCD module receives the clock of an optional external LCD master driver which is used to extend 18 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C nTRST (ARM) This pin is the "not test reset" signal of the ARM. It resets the boundary scan logic of the CPU when low. It is also the reset for the Emulation JTAG interface (not for the application JTAG interface). nWAIT (ARM) 1) 2) This pin outputs the "not wait" signal of the ARM. It is not possible to cause a wait via this pin. OEQ 4) The Output Enable signal connects to the OEQ pin of external memory for read access. Active LOW. P0.0 to P0.7, P1.0 to 1.7 and P2.0 to P2.1 P0.0 to P1.7 are 16 analog ports that are the multiplexed input channels of the ADC. All analog ports P0.0 to P2.1 can also be used as digital input lines. The analog ports P1.2 to P1.7 can also be used as port interrupts. P06COMP Analog port P0.6 is additionally input to the P06 comparator. PFM0, 1 These are the outputs of the PFM0 and PFM1 pulse frequency modulators. PINT0 to PINT5 The port interrupt 0 to 5 inputs serve as inputs to the interrupt controller via the port interrupt module. HW option PM.PINT has to be set to determine which of the possible input pins are used as source of PINT0 to 5. PIPESTAT0 to PIPESTAT2 (ETM) 2) These signals indicate the pipeline status of the ETM. POL Output of the polling module. PWM0 to PWM11 These are the outputs of the PWM module. Some of these PWM signals are directed to two pins. RANGEOUT0, RANGEOUT1 (ARM) 1) These pins output the "ICEBreaker rangeout" signals of the ARM. They indicate that ICEBreaker watch point register 0 or 1 has matched the conditions currently present on the address, data and control busses. RESETQ This bidirectional signal is used to initialize all modules and start program execution. Two comparators distinguish three input levels: - A low level resets all internal modules. - A medium level activates all internal modules and starts program execution. An alarm signal is generated which can be directed to the interrupt controller. - A high level keeps all internal modules active and cancels the alarm signal. The RESETQ input signal must be held low for at least two clock cycles after VDD reaches operating voltage. Internal reset sources output their reset request on the RESETQ pin via an internal open drain pull-down transistor. Thus RESETQ can be wire-ored with external reset sources. The internally limited pull-down current allows direct connection to large capacitors. The connection of such a capacitor (e.g. 10 nF) is recommended to reduce the capacitive influence of the neighboring XTAL2 pin. the LCD driver capability. This input is active if the internal LCD module is configured as slave and the external LCD driver operates as master. LCD-CLK-OUT The clock output of the LCD module provides a clock signal to optional external LCD slave drivers if the internal LCD module is configured as master and the other LCD drivers are slaves. LCD-SYNC-IN The synchronization input of the LCD module receives the sync signal from an optional external LCD master driver. This input is active if the internal LCD module is configured as slave and the external LCD driver serves as master. LCD-SYNC-OUT The synchronization output of the LCD module provides a sync signal to optional external LCD slave drivers if the internal LCD module is configured as master and the other LCD drivers are slaves. LCK This output signal indicates that the PLL has locked. LOCK (ARM) 1) This is the LOCK output signal of the ARM indicating that the processor is performing a "locked" memory access when high. MAS0, MAS1 (ARM) 1) 2) These are ARM output signals used by the processor to indicate to the external memory system when a word transfer or a half-word or a byte length is required. MTI This is a test input line. It is intended for factory test only. The application should not use this signal. MTO This is a test output line. It is intended for factory test only. The application should not use this signal. nEXEC (ARM) 1) This is the "not executed" signal of the ARM indicating that the instruction in the execution unit is not being executed when high. nM0 to nM4 (ARM) 1) These pins output the "not processor mode" signal of the ARM. nMREQ (ARM) 1) 2) This pin outputs the "not memory request" signal of the ARM. The processor requires memory access during the following cycle when low. nOPC (ARM) 1) This pin outputs the "not op-code fetch" signal of the ARM. The processor is fetching an instruction from memory when low. nRESET (ARM) This pin outputs the "not reset" signal of the ARM. This pin is not an input. nRW (ARM) 1) This pin outputs the "not read/write" signal of the ARM. High indicates a processor write cycle, low a read cycle. nTRANS (ARM) 1) This pin outputs the "not memory translate" signal of the ARM. When low, it indicates that the processor is in user mode. Micronas Feb. 10, 2005; 6251-579-1DS 19 CDC 32xxG-C RESETQ must be pulled up by an external pull-up resistor (e.g. 10 k). RWQ 4) This is an interface signal to external memory. SCL0 to SCL1 These are the serial clock lines of the I2C modules. SDA0 to SDA1 These are the serial data lines of the I2C modules. SEG0.0 to SEG8.5 These pin functions serve as segment drivers for a 4:1 multiplexed LCD. SEQ (ARM) 1) 2) This pin outputs the "sequential address" signal of the ARM. High indicates that the address of the next memory cycle will be related to that of the last memory access. SMA to SMG These lines are intended for driving stepper motors. They are the outputs of the SM. Two of these lines together with an external coil form an H-bridge. Thus each of the signals SMA to SMG can drive a two-phase bipolar stepper motor. SMA-COMP0, 1, 2, 3 to SMG-COMP0, 1, 2, 3 These lines are comparator inputs that connect to one line each of the SMA to SMG lines. They serve to distinguish rotation from stand-still during zero detection in each stepper motor. SPI0-CLK-IN, SPI1-CLK-IN The serial synchronous peripheral interface clock input receives the bit clock from an external master, to shift data in or out of SPI0 resp. SPI1 in slave mode. This means that the external master controls the bit stream. SPI0-CLK-OUT, SPI1-CLK-OUT The serial synchronous peripheral interface clock output supplies the bit clock of SPI0 resp. SPI1 to an external slave, to shift data in or out of SPI0 resp. SPI1 in master mode. This means that the internal SPI controls the bit stream. SPI0-D-IN, SPI1-D-IN These are the data input lines of the SPI0 and SPI1 modules. SPI0-D-OUT, SPI1-D-OUT These are the data output lines of the SPI0 and SPI1 modules. T0-OUT The Timer 0 output is connected to the zero output of T0 by a divide-by-2 scaler. The scaler generates a 50% pulse duty factor. T1-OUT to T4-OUT These signals are connected to the overflow outputs of T1 to T4. TBIT (ARM) 1) This pin outputs the TBIT signal of the ARM. High indicates that the processor is executing the THUMB instruction set. TCK (ARM) This pin is the ARM "test clock" input of the application JTAG interface. TDI (ARM) This pin is the ARM "test data input" of the application JTAG interface. DATA SHEET TDO (ARM) This pin is the ARM "test data output" of the application JTAG interface. TEST, TEST2 Pins TEST and TEST2 define the source for the control word fetch during reset. Please refer to section "Core Logic" for detailed information. TEST2 serves to enable the JTAG interface. Refer to section "JTAG Interface" for detailed information. For normal operation with internal code connect TEST and TEST2 to system ground or leave it floating (internal pulldown). TMS (ARM) This pin is the ARM "test mode select" input of the application JTAG interface. TO2 and TO3 Test outputs. TRACECLK (ETM) 2) This is the output of the modified CLK signal of the ETM. TRACEPKT0 to TRACEPKT15 (ETM) 2) This is the trace packet port of the ETM. TRACEPKT15 is pulled low to prevent floating, when full trace mode is enabled. TRACESYNC (ETM) 2) This is the synchronization signal from the ETM, indicating the start of a branch sequence on the trace packet port. U0.0 to U8.5 Universal ports are intended for use as digital I/O or as LCD driver outputs. UART0-RX, UART1-RX These are the receive input lines of UART0 and UART1. Polarity of the signals is settable by HW options UA0 resp. UA1. UART0-TX, UART1-TX These are the data output lines of UART0 and UART1. Polarity of signals can be set by HW options UA0, resp. UA1. UVDD, UVDD1 The pins UVDD and UVDD1 are the positive 5 V supply for the U-Port output stages, for the VDD regulator and the FVDD regulator (see Fig. 2-3 for external connection). It must be buffered by an external capacitor to UVSS, resp. UVSS1. UVSS, UVSS1 The pins UVSS and UVSS1 are the negative power supply for the U-Port output stages, and the ground reference for the VDD and FVDD regulators. They have to be connected to system ground (see Fig. 2-3). VDD This is the output of the internal 2.5V regulator for the internal digital modules (see Fig. 2-3 for external connection). It must be buffered by an external capacitor to VSS. VREF, VREF0, VREF1 These pins are selectable as positive reference inputs for the ADC. The voltage on these pins should be set to a level between 2.56 V and AVDD. VREFINT This pin is the positive reference output of the ADC. The voltage at this pin is generated internally (approx. 2.5 V) and 20 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C WEQ 4) The output signal Write Enable connects to the external memory's WEQ pin and activates it for write access. Active LOW. WP0 to WP9 The wake port inputs are inputs to the port wake module inside the power-saving module. They serve as wake ports during power-saving modes and as port interrupt inputs during CPU-active modes. XTAL1 This is the quartz oscillator or clock input pin (see Fig. 2-3 for external connection). XTAL2 This is the quartz oscillator output pin for two pin oscillator circuits (see Fig. 2-3 for external connection). must be buffered by an external capacitor to AVSS. No DC load is allowed. VSS The pin VSS is the negative supply terminal of the internal digital modules (see Fig. 2-3 for external connection). WAIT This is the positive input to the WAIT comparator. The negative input is VREFINT. The comparator level can be adjusted by an external voltage divider. WAITH This is the output of the WAIT comparator. The hysteresis can be adjusted by an external feedback resistor to the voltage divider connected to the WAIT pin. 1) Trace Bus output. Active in analyzer mode. 2) Trace Bus output. Active in ETM mode. 3) Trace Bus input. Always active. 4) Memory interface signal. Tristate if EMUTRI is high. Please refer to section "Memory Interface" (see Table 34-1 on page 250) for details on interfaces and Trace Bus modes. 2.5. External Components FVDD 3.3 Tantal ESR < 14 470 n Ceramic X7R EVDD0 to 8 3.3 V 9 x 100 n to 150 n 3.3 V/5 V Supply System Ground +5 V Supply FVSS UVDD UVDD1 5V EVSS0 to 8 +5 V Supply 2 x 100 n to 150 n HVDD0 to 3 4 x 100 n to 150 n System Ground UVSS UVSS1 VDD 10 Tantal Low ESR 220 n Ceramic X7R 5V HVSS0 to 3 2.5 V System Ground VSS AVDD 100 n to 150 n Analog Supply XTAL1 18 p 5V 2.5 V VREFINT 10 n, Ceramic AVSS BVDD 150 n Ceramic, X7R +5 V Supply 4.7 k Analog Ground 18 p XTAL2 RESETQ 47 n Resetq System Ground Fig. 2-3: CDC3205G-C: Recommended external supply and quartz connection. To provide effective decoupling and to improve EMC behavior, the small decoupling capacitors must be located as close to the supply pins as possible. The self-inductance of these capacitors and the parasitic inductance and capacitance of the interconnecting traces determine the self-resonant frequency of the decoupling network. Too low a frequency will reduce decoupling effectiveness, will increase RF emissions and may adversely affect device operation. XTAL1 and XTAL2 quartz connections are especially sensitive to capacitive coupling from other PC board signals. It is Micronas Feb. 10, 2005; 6251-579-1DS 21 CDC 32xxG-C strongly recommended to place quartz and oscillation capacitors as close to the pins as possible and to shield the XTAL1 and XTAL2 traces from other signals by embedding them in a VSS trace. DATA SHEET The RESETQ pin adjacent to XTAL2 should be supplied with a 47 nF capacitor, to prevent fast RESETQ transients from being coupled into XTAL2, to prevent XTAL2 from coupling into RESETQ, and to guarantee a time constant of 200 s sufficient for proper wake reset functionality. 2.6. Pin Circuits VSUPOUT VSUPIN Input Logic GNDIN GNDOUT GNDOUT VSUPOUT Fig. 2-4: Input pins Fig. 2-8: Push-pull output pins VSUPOUT VSUPIN GNDIN GNDOUT weak Input Logic VSUPOUT VSUPIN GNDIN GNDOUT weak VSUPL GNDL Input Logic Fig. 2-5: Input pins with pull-down Fig. 2-9: Push-pull I/O pins with switchable pull-down VSUPOUT VSUPH VSUPIN Input Logic GNDIN GNDOUT Regulator Logic GNDH Fig. 2-6: Push-pull I/O pins Fig. 2-10: Regulator pins VSUPOUT VSUPIN Input Logic GNDIN GNDOUT Fig. 2-7: Open-drain I/O 22 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Table 2-2: I/O supply catalog Pin Names XTAL1, XTAL2 WAIT TCK, TDI, TMS EMUTRI, ABORT, EXTERN0, EXTERN1, DBGRQ TEST, TEST2 U-Ports H-Ports P-Ports A31 to A0, ABE, AICU7 to 2, AMCM21 to 23, AMCS1, BWQ0 to 3, CE0Q, CE1Q, D31 to D0, DBGACK, EXTTRIG, FBUSQ, FSYS, MAS0, MAS1, nMREQ, nRESET, nTRST, nWAIT, OEQ, PIPSTAT0 to 2, SEQ, TDO, TRACECLK, TRACEPKT0 to 14, TRACESYNC RESETQ WAITH TRACEPKT15 2-7 2-8 2-9 2-6 HVDD AVDD EVDD HVSS AVSS EVSS HVDD AVDD EVDD HVSS AVSS EVSS 2-5 UVDD UVSS UVDD UVSS Figure 2-4 VSUPOUT UVDD AVDD EVDD GNDOUT UVSS AVSS EVSS VSUPIN UVDD AVDD EVDD GNDIN UVSS AVSS EVSS UVDD AVDD EVDD UVSS AVSS EVSS UVDD UVSS EVDD EVSS Table 2-3: Regulator pin supply catalog Regulator VDD FVDD BVDD Figure 2-10 VSUPH UVDD UVDD AVDD GNDH UVSS UVSS AVSS VSUPL VDD FVDD BVDD GNDL VSS FVSS AVSS Micronas Feb. 10, 2005; 6251-579-1DS 23 CDC 32xxG-C DATA SHEET 24 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 3. Electrical Data 3.1. Absolute Maximum Ratings Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these conditions is not implied. Exposure to absolute maximum ratings conditions for extended periods will affect device reliability. This device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than absolute maximum-rated voltages to this high-impedance circuit. Table 3-1: All voltages listed are referenced to ground (UVSS = UVSS1 = HVSSn = AVSS = 0 V), except where noted. All grounds except VSS must be connected to a low-resistive ground plane close to the IC. Symbol VSUP Parameter Main supply voltage Analog supply voltage SM supply voltage Flash port supply voltage Flash supply voltage Core supply voltage PLL supply voltage ISUP Core supply current Main supply current Flash port supply current Analog supply current SM supply current @TCASE = 105 C, duty factor = 0.71 1) Flash supply current PLL supply current Vin Input voltage Pin Name UVDD, UVDD1 AVDD HVDDn EVDDn FVDD VDD BVDD VDD, VSS, UVDD, UVDD1, UVSS, UVSS1 EVDDn EVSSn AVDD, AVSS HVDDn HVSSn FDD, FVSS BVDD U ports, XTAL, RESETQ, TEST, TEST2 P ports, VREF H ports E ports Iin Io Input current Output current all inputs U ports, E ports, RESETQ, WAITH H ports toshsl Tj 1) Min. -0.3 Max. 6.0 Unit V VREG -0.3 -0.3 -100 4.0 3.0 100 V V mA -100 -20 -250 -50 -20 UVSS - 0.5 100 20 250 50 20 UVDD + 0.7 mA mA mA mA mA V UVSS - 0.5 HVSS - 0.5 EVSS - 0.5 0 -5 -60 AVDD + 0.7 HVDD + 0.7 EVDD + 0.7 2 5 60 indefinite V V V mA mA mA s C Duration of short circuit to UVSS or UVDD, Port SLOW mode enabled Junction temperature under bias U ports, except in DP mode -45 115 This condition represents the worst case load with regard to the intended application. Micronas Feb. 10, 2005; 6251-579-1DS 25 CDC 32xxG-C DATA SHEET Table 3-1: All voltages listed are referenced to ground (UVSS = UVSS1 = HVSSn = AVSS = 0 V), except where noted. All grounds except VSS must be connected to a low-resistive ground plane close to the IC. Symbol Ts Pmax Parameter Storage temperature Maximum power dissipation Pin Name Min. -45 Max. 125 0.8 Unit C W 3.2. Recommended Operating Conditions Do not insert the device into a live socket. Instead, apply power by switching on the external power supply. Keep UVDD = UVDD1 = AVDD during all power-up and power-down sequences. Failure to comply with the above recommendations will result in unpredictable behavior of the device and may result in device destruction. Functional operation of the device beyond those indicated in the "Recommended Operating Conditions" of this specification is not implied, may result in unpredictable behavior of the device and may reduce reliability and lifetime. Table 3-2: All voltages listed are referenced to ground (UVSS = UVSS1 = HVSSn = AVSS = 0 V), except where noted. All grounds except VSS must be connected to a low-resistive ground plane close to the IC. Symbol VSUP Parameter Main supply voltage Analog supply voltage Flash port supply voltage HVSUP dVDD SM supply voltage Ripple, peak-to-peak Pin Name UVDD = UVDD1 = AVDD EVDDn HVDDn UVDD AVDD BVDD FVDD VDD UVDD AVDD XTAL1 4 4 Min. 3.5 Typ. 5 Max. 5.5 Unit V 3 4.75 5 5.5 5.25 200 V V mV dVDD/dt fXTAL fSYS fBUS Vil (see Table 2-2 for a list of input types and their supply voltages) Supply voltage up/down ramping rate XTAL clock frequency CPU clock frequency, PLL on Program storage clock frequency, PLL on Automotive low input voltage 20 5 V/s MHz For a list of available settings see Tables 4-6 and 4-7. U ports H ports P ports U ports, TEST, TEST2 H ports P ports E ports 0.5 x xVDD 0.3 x xVDD V CMOS low input voltage V TTL low input voltage 0.8 V 26 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Table 3-2: All voltages listed are referenced to ground (UVSS = UVSS1 = HVSSn = AVSS = 0 V), except where noted. All grounds except VSS must be connected to a low-resistive ground plane close to the IC. Symbol Vih (see Table 2-2 for a list of input types and their supply voltages) Parameter Automotive high input voltage Pin Name U ports H ports P ports U ports,TEST, TEST2 H ports P ports E ports RESETQ RESETQ Min. 0.86 x xVDD 0.7 x xVDD Typ. Max. Unit V CMOS high input voltage V TTL high input voltage RVil WRVil Reset active input voltage Reset active input voltage during power-saving modes and wake reset Reset inactive and alarm active input voltage Reset inactive and alarm inactive input voltage Reset inactive input voltage during power-saving modes and wake reset Ext. ADC reference input voltage ADC port input voltage referenced to ext. VREF reference ADC port input voltage referenced to int. VREFINT reference 2.2 0.75 0.4 V V V RVim RVih WRVih RESETQ RESETQ RESETQ 1.5 3.2 UVDD - 0.4 V 2.56 0 0 2.3 V V V VREFi PVi VREF P ports AVDD VREF VREFINT V V 3.3. Characteristics Table 3-3: UVSS = UVSS1 = FVSS = HVSSn = EVSSn = AVSS = 0 V, 3.5 V < AVDD = UVDD = UVDD1 < 5.5 V, 4.75 V < HVDDn < 5.25 V, 3 V < EVDDn < 5.5 V, TCASE = 0 C to +70 C, fXTAL = 5 MHz, external components according to Fig. 2-3 (unless otherwise noted) Symbol Package Rthjc 1) Parameter Pin Na. Min. Typ. 1) Max. Unit Test Conditions Thermal resistance from junction to case 15 K/W Typical values describe typical behavior at room temperature (25 C, unless otherwise noted), with typical Recommended Operating Conditions applied, and are not 100% tested. 2) 3) 4) Value may be exceeded with unusual hardware option setting Design value only, the actually observable hysteresis may be lower due to system activity and related supply noise When ERM is active, this time value is increased by 7.5 ns with WEAK ERM setting, by 12.5 ns with NORMAL ERM setting and by 20 ns with STRONG ERM setting. 5) When ERM is active, this time value is decreased by 7.5 ns with WEAK ERM setting, by 12.5 ns with NORMAL ERM setting and by 20 ns with STRONG ERM setting. 6) Measured with external clock. Add typically 120 A for operation on quartz with SR0.XTAL = 0 (Oscillator RUN mode). Micronas Feb. 10, 2005; 6251-579-1DS 27 CDC 32xxG-C DATA SHEET Table 3-3: UVSS = UVSS1 = FVSS = HVSSn = EVSSn = AVSS = 0 V, 3.5 V < AVDD = UVDD = UVDD1 < 5.5 V, 4.75 V < HVDDn < 5.25 V, 3 V < EVDDn < 5.5 V, TCASE = 0 C to +70 C, fXTAL = 5 MHz, external components according to Fig. 2-3 (unless otherwise noted) Symbol Parameter Pin Na. Min. Typ. 1) Max. Unit Test Conditions Supply Currents (CMOS levels on all inputs, i.e. Vil = xVSS 0.3 V and Vih = xVDD 0.3 V, no loads on outputs) UIDDp UIDDpe UIDDf UIDDs UIDDd UIDDw UIDDst UVDD PLL mode supply current, ETM off UVDD PLL mode supply current, ETM on UVDD FAST mode supply current UVDD SLOW mode supply current UVDD DEEP SLOW mode supply current UVDD WAKE mode supply current UVDD STANDBY mode supply current UVDD + UVDD1 UVDD + UVDD1 UVDD + UVDD1 UVDD + UVDD1 UVDD + UVDD1 UVDD + UVDD1 UVDD + UVDD1 0 20 35 60 UIDDi UVDD IDLE mode supply current UVDD + UVDD1 50 75 AIDDa AVDD active supply current AVDD 0.35 55 100 65 110 15 1.3 0.8 50 75 100 775 800 0.6 2 AIDDq EIDDq HIDDq Quiescent supply current AVDD EVDDn Sum of all HVDDn 0 0 0 10 10 40 mA mA mA mA mA A A A A A mA mA A A A fSYS = 24 MHz fSYS = 50 MHz fSYS = 24 MHz fSYS = 50 MHz all modules off 2) all modules off, 2) 6) all modules off, 6) RC and XTAL oscillators off RC oscillator on, XTAL off XTAL oscillator on, RC off 6) RC oscillator on, XTAL off XTAL oscillator on, RC off 6) ADC on, PLL off ADC, buffer and PLL on ADC and PLL off no output activity no output activity, SM module off 1) Typical values describe typical behavior at room temperature (25 C, unless otherwise noted), with typical Recommended Operating Conditions applied, and are not 100% tested. 2) 3) 4) Value may be exceeded with unusual hardware option setting Design value only, the actually observable hysteresis may be lower due to system activity and related supply noise When ERM is active, this time value is increased by 7.5 ns with WEAK ERM setting, by 12.5 ns with NORMAL ERM setting and by 20 ns with STRONG ERM setting. 5) When ERM is active, this time value is decreased by 7.5 ns with WEAK ERM setting, by 12.5 ns with NORMAL ERM setting and by 20 ns with STRONG ERM setting. 6) Measured with external clock. Add typically 120 A for operation on quartz with SR0.XTAL = 0 (Oscillator RUN mode). 28 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Table 3-3: UVSS = UVSS1 = FVSS = HVSSn = EVSSn = AVSS = 0 V, 3.5 V < AVDD = UVDD = UVDD1 < 5.5 V, 4.75 V < HVDDn < 5.25 V, 3 V < EVDDn < 5.5 V, TCASE = 0 C to +70 C, fXTAL = 5 MHz, external components according to Fig. 2-3 (unless otherwise noted) Symbol Inputs Vilha Vihla Vilha-Vihla Vilhc Vihlc Vilhc-Vihlc Ii Automotive input low to high threshold voltage Automotive input high to low threshold voltage Automotive input hysteresis CMOS input low to high threshold voltage CMOS input high to low threshold voltage CMOS input hysteresis Input leakage current U ports H ports P ports P06, WAIT VREF E ports TEST, TEST2 E ports E-DB U ports H ports P ports TEST, TEST2 U ports H ports P ports 0.68 x xVDD 0.53 x xVDD 0.1 x xVDD 0.5 x xVDD 0.3 x xVDD 0.1 x xVDD -1 -10 -1 -0.2 -1 -1 10 10 -220 100 100 -100 0.76 x xVDD 0.61 x xVDD 0.15 x xVDD 0.6 x xVDD 0.4 x xVDD 0.2 x xVDD 0.84 x xVDD 0.69 x xVDD 0.2 x xVDD 0.7 x xVDD 0.5 x xVDD 0.3 x xVDD 1 10 1 0.2 1 1 220 220 -10 A A V V V V V V A 0 < Vi < UVDD 0 < Vi < HVDD 0 < Vi < AVDD 0 < Vi < AVDD 0 < Vi < AVDD 0 < Vi < EVDD Vi = UVDD Vi = EVDD, when unused Vi = 0, when unused 4.5V < xVDD < 5.5V, 3) (see Table 2-2 for a list of input types and their supply voltages) 4.5V < xVDD < 5.5V, 3) (see Table 2-2 for a list of input types and their supply voltages) Parameter Pin Na. Min. Typ. 1) Max. Unit Test Conditions Ipd Input pull-down current Ipu Input pull-up current Outputs (4.5 V < UVDD = EVDD < 5.5 V) Vol Port low output voltage U ports, E ports RESETQ H ports 0.125 0.4 V Io = 2 mA 0.45 V Io = 27 mA Io = 40 mA @ TCASE = -40 C Io = 30 mA @ TCASE = 25 C Vol 1) Difference of Vol values within one SM module H ports 50 mV Typical values describe typical behavior at room temperature (25 C, unless otherwise noted), with typical Recommended Operating Conditions applied, and are not 100% tested. 2) 3) 4) Value may be exceeded with unusual hardware option setting Design value only, the actually observable hysteresis may be lower due to system activity and related supply noise When ERM is active, this time value is increased by 7.5 ns with WEAK ERM setting, by 12.5 ns with NORMAL ERM setting and by 20 ns with STRONG ERM setting. 5) When ERM is active, this time value is decreased by 7.5 ns with WEAK ERM setting, by 12.5 ns with NORMAL ERM setting and by 20 ns with STRONG ERM setting. 6) Measured with external clock. Add typically 120 A for operation on quartz with SR0.XTAL = 0 (Oscillator RUN mode). Micronas Feb. 10, 2005; 6251-579-1DS 29 CDC 32xxG-C DATA SHEET Table 3-3: UVSS = UVSS1 = FVSS = HVSSn = EVSSn = AVSS = 0 V, 3.5 V < AVDD = UVDD = UVDD1 < 5.5 V, 4.75 V < HVDDn < 5.25 V, 3 V < EVDDn < 5.5 V, TCASE = 0 C to +70 C, fXTAL = 5 MHz, external components according to Fig. 2-3 (unless otherwise noted) Symbol Voh Parameter Port high output voltage Pin Na. U ports E ports H ports Min. UVDD - 0.4 EVDD - 0.4 HVDD - 0.55 HVDD - 0.125 Typ. 1) Max. Unit V Test Conditions Io = -2 mA V Io = -27 mA Io = -40 mA @ TCASE = -40 C Io = -30 mA @ TCASE = 25 C Voh dVoH/dt Difference of Voh values within one SM module H-Port slew rate with inductive load H ports H ports 50 by first order approximation defined by the quotient of the inductive load current and the external capacitances on the port pin -0.05 1/3x UVDD - 0.05 2/3x UVDD - 0.05 UVDD - 0.05 0.3 -0.3 0.05 1/3x UVDD + 0.05 2/3x UVDD + 0.05 UVDD + 0.05 mV V/ns LVol LVo1 LCD port zero output voltage LCD port low output voltage U ports U ports V V no load no load LVo2 LCD port high output voltage LCD port full output voltage Internal LCD-low supply short circuit current Internal LCD-high supply short circuit current Port FAST short circuit current Port SLOW short circuit current Port SLOW short circuit current, DP mode U ports V no load LVoh LIo1 LIo2 U ports U ports V mA no load pin short to 2 / 3 x UVDD pin short to UVSS U ports 0.3 -0.3 mA pin short to UVDD pin short to 1 / 3 x UVDD Ishf Ishs Ishsd U ports U ports U ports 14 3.7 7.5 23 5.5 11 mA mA mA pin short to UVDD or UVSS, Port FAST mode pin short to UVDD or UVSS, Port SLOW mode pin short to UVDD, Port SLOW and Double PullDown modes Typical values describe typical behavior at room temperature (25 C, unless otherwise noted), with typical Recommended Operating Conditions applied, and are not 100% tested. 2) 3) 4) 1) Value may be exceeded with unusual hardware option setting Design value only, the actually observable hysteresis may be lower due to system activity and related supply noise When ERM is active, this time value is increased by 7.5 ns with WEAK ERM setting, by 12.5 ns with NORMAL ERM setting and by 20 ns with STRONG ERM setting. 5) When ERM is active, this time value is decreased by 7.5 ns with WEAK ERM setting, by 12.5 ns with NORMAL ERM setting and by 20 ns with STRONG ERM setting. 6) Measured with external clock. Add typically 120 A for operation on quartz with SR0.XTAL = 0 (Oscillator RUN mode). 30 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Table 3-3: UVSS = UVSS1 = FVSS = HVSSn = EVSSn = AVSS = 0 V, 3.5 V < AVDD = UVDD = UVDD1 < 5.5 V, 4.75 V < HVDDn < 5.25 V, 3 V < EVDDn < 5.5 V, TCASE = 0 C to +70 C, fXTAL = 5 MHz, external components according to Fig. 2-3 (unless otherwise noted) Symbol Parameter Pin Na. Min. Typ. 1) Max. Unit Test Conditions References and Comparators, AVDD Section VREFINT tREFINT VREFINT generator reference output voltage VREFINT generator setup time after power-up on AVDD, or on leaving SLOW or DEEP SLOW mode P06 comparator reference voltage P06 comparator hysteresis, symmetrical to VREFP06 WAIT comparator reference voltage WAIT comparator low output voltage WAIT comparator high output voltage P06, WAIT comparator delay time VREFINT VREFINT 2.39 2.49 500 V s external load current < 1 A VREFP06 P06VlhP06Vhl VREFW P06 P06 WAIT 0.49 x AVDD 0.02 x AVDD 0.98 x VREFINT 0.51 x AVDD 0.05 x AVDD 1.02 x VREFINT V V V 3) VWol VWoh tACDEL WAITH WAITH P06 WAIT AVDD - 0.4 V 0.4 V V 4.5 V < xVDD < 5.5 V Io = 50 A 4.5 V < xVDD < 5.5 V Io = -50 A overdrive = 50 mV 1 s References and Comparators, UVDD Section VBG VREFR RVlhRVhl WRVihl VBG generator reference output voltage RESET comparator reference voltage RESET comparator hysteresis, symmetrical to VREFR Reset active high to low threshold voltage during power-saving modes and wake reset ALARM comparator reference voltage ALARM comparator hysteresis, symmetrical to VREFA UVDD power-on reset threshold RESETQ RESETQ RESETQ 2.25 0.45 x VBG 0.25 0.5 2.5 2.75 0.45 x VBG 0.375 1.2 V V V V 3) VREFA AVlhAVhl VREFPOR RESETQ RESETQ UVDD 1.1 x VBG 0.1 1.125 x VBG 1.1 x VBG 0.2 1.125 x VBG V V V 3) 1) Typical values describe typical behavior at room temperature (25 C, unless otherwise noted), with typical Recommended Operating Conditions applied, and are not 100% tested. 2) 3) 4) Value may be exceeded with unusual hardware option setting Design value only, the actually observable hysteresis may be lower due to system activity and related supply noise When ERM is active, this time value is increased by 7.5 ns with WEAK ERM setting, by 12.5 ns with NORMAL ERM setting and by 20 ns with STRONG ERM setting. 5) When ERM is active, this time value is decreased by 7.5 ns with WEAK ERM setting, by 12.5 ns with NORMAL ERM setting and by 20 ns with STRONG ERM setting. 6) Measured with external clock. Add typically 120 A for operation on quartz with SR0.XTAL = 0 (Oscillator RUN mode). Micronas Feb. 10, 2005; 6251-579-1DS 31 CDC 32xxG-C DATA SHEET Table 3-3: UVSS = UVSS1 = FVSS = HVSSn = EVSSn = AVSS = 0 V, 3.5 V < AVDD = UVDD = UVDD1 < 5.5 V, 4.75 V < HVDDn < 5.25 V, 3 V < EVDDn < 5.5 V, TCASE = 0 C to +70 C, fXTAL = 5 MHz, external components according to Fig. 2-3 (unless otherwise noted) Symbol tUCDEL Parameter RESET, ALARM, comparator delay time Pin Na. RESETQ Min. Typ. 1) Max. 1 Unit s Test Conditions overdrive = 50 mV References and Comparators, HVDD Section VREFSM SM comparator reference voltage H00, H04, H20, H24, H32, H40, H70 H00, H04, H20, H24, H32, H40, H70 1/9x HVDD - 0.07 1/9x HVDD + 0.07 V tHCDEL SM comparator delay time 100 ns overdrive = 50 mV VDD Regulator VDD_ro Regulator output voltage VDD 1.02 x VBG - 30 mV 1.02 x VBG - 105mV IDD_rlim IDD_rlimr tVDD_su Regulator internal output current limit Regulator internal output current limit during reset Regulator setup time after power-up on UVDD VDD VDD VDD 120 24 275 55 120 1.02 x VBG + 30 mV 1.02 x VBG - 0 mV 460 92 400 V DEEP SLOW mode V PLL mode, fSYS = 50 MHz mA mA s FAST mode BVDD Regulator BVDD_ro Regulator output voltage BVDD VREFINT - 25 mV 17 40 70 VREFINT + 25 mV 70 230 V PLLC.PMF > 0 BIDD_rlim tBVDD_su Regulator internal output current limit Regulator setup time after setting PLLC.PMF > 0 BVDD BVDD mA s PLLC.PMF > 0 1) Typical values describe typical behavior at room temperature (25 C, unless otherwise noted), with typical Recommended Operating Conditions applied, and are not 100% tested. 2) 3) 4) Value may be exceeded with unusual hardware option setting Design value only, the actually observable hysteresis may be lower due to system activity and related supply noise When ERM is active, this time value is increased by 7.5 ns with WEAK ERM setting, by 12.5 ns with NORMAL ERM setting and by 20 ns with STRONG ERM setting. 5) When ERM is active, this time value is decreased by 7.5 ns with WEAK ERM setting, by 12.5 ns with NORMAL ERM setting and by 20 ns with STRONG ERM setting. 6) Measured with external clock. Add typically 120 A for operation on quartz with SR0.XTAL = 0 (Oscillator RUN mode). 32 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Table 3-3: UVSS = UVSS1 = FVSS = HVSSn = EVSSn = AVSS = 0 V, 3.5 V < AVDD = UVDD = UVDD1 < 5.5 V, 4.75 V < HVDDn < 5.25 V, 3 V < EVDDn < 5.5 V, TCASE = 0 C to +70 C, fXTAL = 5 MHz, external components according to Fig. 2-3 (unless otherwise noted) Symbol Parameter Pin Na. Min. Typ. 1) Max. Unit Test Conditions FVDD Regulator FVDD_ro Regulator output voltage FVDD VBG x 1.34- 40 mV VBG x 1.34- 170mV FIDD_rlim tFVDD_su Regulator internal output current limit Regulator setup time after power-up on UVDD FVDD FVDD 52 120 100 VBG x 1.34 + 40 mV VBG x 1.34 - 40 mV 200 330 V no load V IFVDD = -40 mA mA s IFVDD = -40 mA ADC (conversion reference VREFC either equal to external reference VREF or internal reference VREFINT) LSB INL LSB value Integral non-linearity: difference between the output of an actual ADC and the line best fitting the output function (best-fit line) Zero error: difference between the output of an ideal and an actual ADC for zero input voltage Full-scale error: difference between the output of an ideal and an actual ADC for full-scale input voltage Total unadjusted error: maximum sum of integral non-linearity, zero error and full-scale error Quantization error: uncertainty because of ADC resolution -2.5 VREFC / 1024 2.5 V LSB 2.4 V < VREFC < AVDD, 4.5 V < AVDD < 5.5 V ZE -1 1 LSB 2.4 V < VREFC < AVDD, 4.5 V < AVDD < 5.5 V FSE -1 1 LSB 2.4 V < VREFC < AVDD, 4.5 V < AVDD < 5.5 V TUE -3.5 3.5 LSB 2.4 V < VREFC < AVDD, 4.5 V < AVDD < 5.5 V QE -0.5 0.5 LSB 2.4 V < VREFC < AVDD, 4.5 V < AVDD < 5.5 V Typical values describe typical behavior at room temperature (25 C, unless otherwise noted), with typical Recommended Operating Conditions applied, and are not 100% tested. 2) 3) 4) 1) Value may be exceeded with unusual hardware option setting Design value only, the actually observable hysteresis may be lower due to system activity and related supply noise When ERM is active, this time value is increased by 7.5 ns with WEAK ERM setting, by 12.5 ns with NORMAL ERM setting and by 20 ns with STRONG ERM setting. 5) When ERM is active, this time value is decreased by 7.5 ns with WEAK ERM setting, by 12.5 ns with NORMAL ERM setting and by 20 ns with STRONG ERM setting. 6) Measured with external clock. Add typically 120 A for operation on quartz with SR0.XTAL = 0 (Oscillator RUN mode). Micronas Feb. 10, 2005; 6251-579-1DS 33 CDC 32xxG-C DATA SHEET Table 3-3: UVSS = UVSS1 = FVSS = HVSSn = EVSSn = AVSS = 0 V, 3.5 V < AVDD = UVDD = UVDD1 < 5.5 V, 4.75 V < HVDDn < 5.25 V, 3 V < EVDDn < 5.5 V, TCASE = 0 C to +70 C, fXTAL = 5 MHz, external components according to Fig. 2-3 (unless otherwise noted) Symbol AE Parameter Absolute error: difference between the actual input voltage and the full-scale weighted equivalent of the binary output code, all error sources included Conversion range Conversion result P ports Pin Na. Min. -4 Typ. 1) Max. 4 Unit LSB Test Conditions 2.4 V < VREFC < AVDD, 4.5 V < AVDD < 5.5 V R A AVSS INT (Vin / LSB) 000 VREFC V hex 2.4 V < VREFC < AVDD AVSS < Vin < VREFC hex 3FF hex s s pF Vin AVSS Vin VREFC TSAMP = 0, fIO = 10 MHz buffer off buffer on tc ts Ci Conversion time Sample time Internal sampling capacitance during sampling period Internal serial resistance during sampling period 4 2 7.5 2.5 7 Ri kOhm buffer off PLL and ERM tSUPLL dtPLL PLL locking time I/O clock uncertainty due to PLL jitter, short term and long term I/O clock phase shift due to ERM action, short term and long term 0 0 0 RC Oscillator fRC Output frequency 20 35 50 kHz 2.5 100 s ns @ fXTAL = 4 MHz, fSYS = 16 MHz ERM off dtERM 7.5 12.5 20 ns ERM on, WEAK setting ERM on, NORMAL setting ERM on, STRONG setting Clock Supervision fSUP 1) Clock supervision threshold frequency XTAL1 70 350 kHz Typical values describe typical behavior at room temperature (25 C, unless otherwise noted), with typical Recommended Operating Conditions applied, and are not 100% tested. 2) 3) 4) Value may be exceeded with unusual hardware option setting Design value only, the actually observable hysteresis may be lower due to system activity and related supply noise When ERM is active, this time value is increased by 7.5 ns with WEAK ERM setting, by 12.5 ns with NORMAL ERM setting and by 20 ns with STRONG ERM setting. 5) When ERM is active, this time value is decreased by 7.5 ns with WEAK ERM setting, by 12.5 ns with NORMAL ERM setting and by 20 ns with STRONG ERM setting. 6) Measured with external clock. Add typically 120 A for operation on quartz with SR0.XTAL = 0 (Oscillator RUN mode). 34 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Table 3-3: UVSS = UVSS1 = FVSS = HVSSn = EVSSn = AVSS = 0 V, 3.5 V < AVDD = UVDD = UVDD1 < 5.5 V, 4.75 V < HVDDn < 5.25 V, 3 V < EVDDn < 5.5 V, TCASE = 0 C to +70 C, fXTAL = 5 MHz, external components according to Fig. 2-3 (unless otherwise noted) Symbol Parameter Pin Na. Min. Typ. 1) Max. Unit Test Conditions SPI (Fig. 3-1, Fig. 3-2) tso tho tsoci thoci tsoce thoce tsi thi CAN tIOd Internal I/O delay time CAN-RX, CAN-TX 35 4) ns @ Cl = 30 pF, Port FAST mode, UVDD 4.5 V Data out setup time from internal clock out Data out hold time from internal clock out Data in setup time to internal clock out Data in hold time from internal clock out Data out setup time from external clock in Data out hold time from external clock in Data in setup time to external clock in Data in hold time from external clock in SPI-DOUT SPI-DOUT SPI-D-IN SPI-D-IN SPI-DOUT SPI-DOUT SPI-D-IN SPI-D-IN 2.5 / fIO + 15 5) 1/ fIO + 25 4) 1/ fIO 4) -5 35 0 3.5 / fIO + 35 4) +5 ns ns ns ns ns ns ns ns @ Cl = 30 pF, Port FAST mode, UVDD 4.5 V DIGITbus (Fig. 3-3) tbtj tfed Bit time jitter Falling edge delay from nominal pulse falling edge DIGITOUT DIGITOUT 15 tBIT / 64 + 40 4) ns ns rising edges, internal clock master, ERM on @ Cl = 30 pF, Port FAST mode, UVDD 4.5 V 1) Typical values describe typical behavior at room temperature (25 C, unless otherwise noted), with typical Recommended Operating Conditions applied, and are not 100% tested. 2) 3) 4) Value may be exceeded with unusual hardware option setting Design value only, the actually observable hysteresis may be lower due to system activity and related supply noise When ERM is active, this time value is increased by 7.5 ns with WEAK ERM setting, by 12.5 ns with NORMAL ERM setting and by 20 ns with STRONG ERM setting. 5) When ERM is active, this time value is decreased by 7.5 ns with WEAK ERM setting, by 12.5 ns with NORMAL ERM setting and by 20 ns with STRONG ERM setting. 6) Measured with external clock. Add typically 120 A for operation on quartz with SR0.XTAL = 0 (Oscillator RUN mode). Micronas Feb. 10, 2005; 6251-579-1DS 35 CDC 32xxG-C DATA SHEET SPI-CLK-OUT tso tho SPI-D-OUT tsoci SPI-D-IN Fig. 3-1: SPI: Send and receive data with internal clock. Timing is valid for inverted clock too (data valid at positive edge). thoci SPI-CLK-IN tsi SPI-D-IN tsoce thoce SPI-D-OUT Fig. 3-2: SPI: Send and receive data with external clock. Timing is valid for inverted clock too (data valid at positive edge). thi tBIT DIGIT-IN DIGIT-OUT tfed nominal pulse tNPL tNPL: Nominal programmed pulse length. Depends on programmed phase, baud rate and transmitted sign (0, 1, T). Should be 1/4 for sign 0, 1/2 for sign 1 and 3/4 for sign T of tBIT. Fig. 3-3: DIGITbus I/O timing tbtj tbtj 36 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 3.4. Recommended Quartz Crystal Characteristics Table 3-4: 3.5 V < UVDD < 5.5 V, external components according to Fig. 2-3, unless otherwise noted Symbol fP R1 Parameter Parallel resonance frequency @ CL = 12 pF Series resonance resistance for 50 ms oscillation start-up time and proper function @ CL = 12 pF @ fP = 4 MHz Min. 4 Typ. Max. 5 Unit MHz Test Conditions @ fP = 5 MHz 340 380 210 270 240 280 140 180 18 Ohm START-UP START-UP, 4.5 V < UVDD < 5.5 V RUN RUN, 4.5 V < UVDD < 5.5 V START-UP START-UP, 4.5 V < UVDD < 5.5 V RUN RUN, 4.5 V < UVDD < 5.5 V CEXT External oscillation capacitances, connected to VSS pF Micronas Feb. 10, 2005; 6251-579-1DS 37 CDC 32xxG-C DATA SHEET 38 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 4. CPU and Clock System 4.1. ARM7TDMITM CPU The CPU is an ARM7TDMI 32-bit RISC processor. This is a member of the Advanced RISC Machines (ARM) family. The ARM7TDMI is a 3-stage pipeline machine and supports a 4-Gbit address range. In addition to the 32-bit standard ARM instruction set, the ARM7TDMI supports the 16-bit Thumb instruction set which allows a higher code density. It includes a 64-bit result multiplier and a JTAG interface with an embedded debug module. 4.1.1. CPU States The ARM7TDMI CPU allows operation in two states: - ARM state: 32-bit instructions - Thumb state: 16-bit instructions After reset and exceptions, ARM state is active. 4.2. Operating Modes To adapt to the large variety of CPU speed and current consumption requirements, the device offers a number of operating modes: - CPU-active modes, where the CPU is clocked at selectable speeds - Power-saving modes, where the CPU is kept reset and where only certain circuit portions are powered. Fig. 4-1 shows how the various modes are accessed, in an operating modes state diagram. Power-up Global Reset with Ports Global Reset w/o Ports <50 ms (if 4/5MHz XTAL was off) ~0.5 ms (if 4/5MHz XTAL stays on) <50 ms (if 4/5MHz XTAL was off) ~0.5 ms (if 4/5MHz XTAL stays on) CPUM=WAKE/STBY 0 WAKE and STANDBY RESETQ, RTC, Wake Ports RTC, Wake Ports CPUM=IDLE 0 IDLE RESETQ CPUM=DEEP SLOW FAST CPUM=FAST CPUM=SLOW CPUM=FAST CPUM=PLL CPUM=FAST 128/fXTAL 0 128/fXTAL 0 ~100 s ~s PLL SLOW DEEP SLOW All reset sources All reset sources All reset sources Fig. 4-1: Operating modes state diagram Micronas Feb. 10, 2005; 6251-579-1DS 39 CDC 32xxG-C 4.2.1. CPU-Active Modes The CPU can be operated in five different CPU-active modes (Table 4-1). Core modules that are also affected by CPUactive modes are: 1. Interrupt Controller with all internal and external interrupts 2. RAM, ROM/Flash and DMA 3. Watchdog Table 4-1 shows the operability of the peripheral modules in the various CPU-active modes. When switching between modes, neither interrupts (see Section 11.4.4. on page 96) nor DMA (see Section 22.3. on page 146) accesses are allowed, to prevent undefined behavior of the clock system. 4.2.1.1. FAST Mode After reset the CPU is in FAST mode. The CPU clock and the I/O clock both equal the oscillator frequency fXTAL. Internal clock frequencies higher than fXTAL are not available in this mode. Modules requiring f0 = 2fXTAL for operation will not work properly, as f0 is set to f1 = fXTAL. Returning CPU from any other CPU-active mode to FAST mode is done by selecting the appropriate mode in the standby registers field SR1.CPUM (Table 4-3). 4.2.1.2. PLL Modes To increase CPU performance, a PLL allows to multiply fXTAL. The CPU will operate at this higher frequency fSYS and its speed is automatically reduced only for accesses to slower modules (ROM/Flash, I/O). Table 4-6 gives recommended settings for control registers and the various resulting operating frequencies for the PLL mode. These recommended settings achieve f0 = 2*fXTAL, f1 = fXTAL and so forth, for unlimited operation of peripheral modules. A PLL2 mode allows bypassing of the first stage of the divider chain. It allows a clock system with fSYS = n*fXTAL and f0 = f1 = fXTAL for special applications, where the unlimited operation of peripheral circuits has to be sacrificed (see Table 4-7 for settings). In both PLL modes, the EMI reduction module (ERM) can be operated, which reduces electromagnetic energy emission (see Section 4.5. on page 47). Activating the PLL modes is done in FAST mode by the following routine: 1. For initialization, choose a pair of settings for the clock multiplication factor and the clock prescaler from Tables 4-6 or 4-7 and write them to PLLC.PMF and IOC.IOP. 2. When coming from SLOW or DEEP SLOW mode, allow tREFINT to elapse for VREFINT and BVDD to set up. In all other cases, wait the time of tBVDD_su for BVDD to set up. 3. Wait for at least tSUPLL before checking PLLC.LCK to be set, to make sure that the PLL has locked. 4. Disable ICU and DMA, if active. 5. Enable PLL mode by writing 0x03, or PLL2 mode by writing 0x07 to SR1.CPUM (32-bit access only). 6. As the system frequency divider and the prescaler need some time to synchronize, the PLL mode is not active until PLLC.PLLM reads as 1. DATA SHEET 7. At this point the ERM may be activated (see Section 4.5.3. on page 47) and ICU and DMA may be (re-)enabled. Returning to FAST mode is done by the following routine: 1. Deactivate the ERM, if active (see Section 4.5.4. on page 47). 2. Disable ICU and DMA, if active. 3. Return to FAST mode by setting SR1.CPUM to 0x01 (32bit access only). 4. Wait for PLLC.PLLM to read as 0. 5. Now the ICU and DMA may be (re-)enabled and the program may resume. Attention: The PLL modes must be entered and left only via FAST mode. The registers PLLC.PMF and IOC.IOP may only be changed in FAST mode. To reduce the power consumption in other CPU-active modes than PLL modes, the registers PLLC.PMF and IOC.IOP should be programmed to zero. 4.2.1.3. SLOW Mode To considerably reduce power consumption, the user can reduce the internal CPU clock frequency to 1/128 of the normal fXTAL value. In this SLOW mode, program execution is reduced to 1/128 of fXTAL. Some modules must not be operated during SLOW mode (e.g. CAN). Refer to module sections for details (see Table 4-1 on page 41). Internal clock frequencies higher than fXTAL are not available in this mode. Modules requiring f0 = 2*fXTAL for operation will not work properly, as f0 is set to f1 = fXTAL. For switching between SLOW and FAST modes, use the following routine: 1. Disable ICU and DMA, if active. 2. Select the desired mode in the standby registers field CPUM (Table 4-3). The new fBUS is effective immediately. 3. Now the ICU and DMA may be (re-)enabled and the program may resume (no waiting time). 4.2.1.4. DEEP SLOW Mode To further reduce power consumption beyond SLOW mode, DEEP SLOW mode also disables most of the internal peripheral clocking system. Table 4-1 shows which peripheral modules can be operated in DEEP SLOW mode. Only peripheral module clocks f5 and slower are available from the divider chain. T0 can be operated only with this limitation. For switching between DEEP SLOW and FAST modes, use the routine given for SLOW mode. 4.2.2. Power-Saving Modes All power-saving modes are activated by the CPU. The complete core logic will immediately terminate operation and power will be removed. The result is a device current consumption that is greatly reduced, to the amount of leakage currents. 40 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Table 4-1: Operability of modules in CPU-active modes Module Core Digital Watchdog IRQ Interrupt Controller Unit FIQ Interrupt Logic Port Interrupts Port Wake Module Memory Patch Module Analog A/D Converter ALARM, P06 and WAIT Comparators LCD Module Communication DMA DMA Timer, GBus UART SPI CAN DIGITbus I2C Input & Output Ports Stepper Motor Module PWM PFM Audio Module Clock Outputs Timers & Counters Capture Compare Module Timers RTC/Polling Module 1) 1) 1) 1) 2) 1) 2) 3) 4) 3) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 3) 1) 1) 3) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 4) 1) 4) 3) 4) 3) 1) 1) 1) 1) 1) 1) 3) PLL PLL2 FAST SLOW DEEP SLOW 1) Possibly affected by f0 equaling f1 2) Avoid write access to CCxI 3) Only clocks f5 and slower are available 4) from Clock Divider Don't access registers or CAN RAM Micronas Feb. 10, 2005; 6251-579-1DS 41 CDC 32xxG-C Table 4-1: Operability of modules in CPU-active modes Module Miscellaneous JTAG Embedded Trace Module PLL PLL2 FAST SLOW DATA SHEET DEEP SLOW 1) Possibly affected by f equaling f 0 1 2) Avoid write access to CCxI 3) Only clocks f5 and slower are available 4) Don't access registers or CAN RAM from Clock Divider However, a means to leave these modes has to be provided. As the CPU is no longer active, either an external or internal WAKE signal has to be generated. The external WAKE costs no device current, but to generate an internal WAKE requires an internal oscillator and a real-time clock (RTC) to run, which will cost a small amount of supply current. Please note that inadvertently entering a power-saving mode, (e.g., by an external electrical overstress (EOS) condition, when no wake source has been configured previously as recovery path from this state), renders the device locked in this power-saving mode. Only a RESETQ pin reset or a complete power removal and reapplication recovers the device from this state. Sufficient external shielding measures must be taken to avoid this hazard. Table 4-2: Power-saving modes and related functionality versus CPU-active modes Operating Mode Modules That Can Be Activated SRAM, CAN-RAM data lost data lost Port Registers reset reset Available Wake Sources Wake ports Wake ports and RTC PowerSaving Modes WAKE STANDBY Port wake module All WAKE mode modules plus: - 4M XTAL or 20..50k RC oscillator - Real-time clock - Polling module All STANDBY mode modules plus an auxiliary VDD regulator that keeps RAM and port registers alive. Other modules according to Table 4-1 are not supported. In principle all, for limitations see Table 4-1 IDLE data retained state retained Wake ports and RTC CPU-Active Modes active active Wake sources usable as interrupt 4.2.2.1. WAKE Mode WAKE mode is the most current-saving operation mode. All device circuits are stopped or powered down except the port wake module (Table 4-2). The port wake module allows the CPU to configure up to ten fixed device ports (see the device pinout for details) as wake ports (WP). To prepare for WAKE mode, the CPU has to switch off the RTC and to configure the desired wake port(s) (see chapter "Power Saving Module", sections "Port Wake Module" and "RTC Module"). To enter WAKE mode, the CPU selects WAKE/STBY in register SR1.CPUM. The device will immediately enter WAKE mode by resetting all circuitry, stopping all clocks, and powering down all regulators and analog circuitry. As long as all wake port inputs are kept at CMOS input levels (Vil = xVSS 0.3 V and Vih = xVDD 0.3 V), the supply currents will be minimal. The device may be kept in this state indefinitely. To exit WAKE mode, the previously configured wake port has to switch. Immediately a "wake reset" sequence will be started internally that pulls the RESETQ pin low and releases it as soon as all internal reset sources have become inactive. See chapter "Core Logic" for details on internal reset sources. After reset, the CPU starts in FAST mode, as usual. 4.2.2.2. STANDBY Mode STANDBY mode allows to configure an internal wake source that wakes after a preselected period. As clock sources, either a current-saving, but imprecise internal RC oscillator, or the precise, but more current-consuming XTAL oscillator are selectable. Beside the port wake module, these circuits and the RTC are kept alive (Table 4-2). 42 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C modes, an auxiliary VDD regulator allows to maintain some core functionality (Table 4-2): - the internal SRAM and CAN-RAM keeps its programmed data - all U-, P- and H-Port registers (see chapter "Ports") keep their programmed state (LCD ports will output a low level). Leakage currents in these additionally powered modules add to the device current consumption. To prepare for IDLE mode, the CPU has to configure the desired RTC wake clock (see chapter "Power Saving Module", section "RTC Module"), the desired wake port(s) (see chapter "Power Saving Module", section "Port Wake Module") and the port registers as desired. To enter IDLE mode, the CPU selects IDLE in register SR1.CPUM. The device will immediately enter IDLE mode by resetting all circuitry except the port registers, stopping the unused clocks, and powering down all main regulators and remaining analog circuitry, but not the auxiliary VDD regulator. As long as all U-, P- and H-Ports, that are configured as inputs, are kept at CMOS input levels (Vil = xVSS 0.3 V and Vih = xVDD 0.3 V), the supply currents will amount to the requirement of the oscillator(s), the RTC and polling modules and mere leakage currents flowing mainly in SRAM. To exit IDLE mode, the previously configured wake source has to switch. Immediately a Wake Reset sequence will be started internally that pulls the RESETQ pin low and releases it as soon as all internal reset sources have become inactive, but port registers and SRAM will be exempt from being reset. See chapter "Core Logic" for details on internal reset sources. After reset, the CPU starts in FAST mode, as usual. The RTC allows the CPU to select from one-second to oneday clocks (see section "Power Saving Module" for details) as wake signal. Beside serving as wake source, the CPU may use the RTC as real time clock that is not halted by resets. A polling module, driven by a selectable RTC clock, may be configured to generate a polling pulse on H0.2 and sample the wake ports immediately after. Thus a periodical polling of wake ports may be achieved, with no continuous power consumption in external circuitry. To prepare for STANDBY mode, the CPU has to configure the desired RTC wake clock (see chapter "Power Saving Module", section "RTC Module"), in addition to the desired wake port(s), see chapter "Power Saving Module", section "Port Wake Module". To enter STANDBY mode, the CPU selects WAKE/STBY in register SR1.CPUM. The device will immediately enter STANDBY mode by resetting all circuitry, stopping the unused clocks, and powering down all regulators and remaining analog circuitry. As long as all wake port inputs are kept at CMOS input levels (Vil = xVSS 0.3 V and Vih = xVDD 0.3 V), the supply currents will only amount to the requirement of the oscillator(s) and the slow-clocked RTC and polling modules. To exit STANDBY mode, the previously configured wake source has to switch. Immediately a Wake Reset sequence will be started internally that pulls the RESETQ pin low and releases it as soon as all internal reset sources have become inactive. See chapter "Core Logic" for details on internal reset sources. After reset, the CPU starts in FAST mode, as usual. 4.2.2.3. IDLE Mode IDLE mode allows usage of the same wake sources as STANDBY mode. But in contrast to WAKE and STANDBY 4.3. Clock System The IC contains a quartz oscillator circuit that only requires external connection of a quartz and of two oscillation capacitors. Its start-up and run properties are controllable by SW. See section "Core Logic" for details. The oscillator clock fXTAL drives a clock system that supplies the various modules with its specific clock (Fig. 4-2). A frequency multiplying PLL allows to select the system clock fSYS to be higher than fXTAL for high speed CPU and module operation. A divider chain divides fIO down to supply peripheral module clocks f0 to f17. Module clock selection is software defined in some cases, hardware or HW option defined in other cases. The module descriptions give details. The standby register field SR1.CPUM selects the operating mode (Table 4-3). Micronas Feb. 10, 2005; 6251-579-1DS 43 CDC 32xxG-C Table 4-3: Operating mode selection and effect on clocks SR1.CPUM Operating Mode SLOW FAST DEEP SLOW PLL WAKE /STBY IDLE rsvd PLL2 fBUS fIO f0 f1 fXTAL = 4/5MHz ON_5 & DATA SHEET 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fXTAL/ 128 fXTAL fXTAL/ 128 n fXTAL n fXTAL fXTAL/ 128 fXTAL fXTAL/ 128 n/m fXTAL n/m fXTAL fXTAL fXTAL fXTAL PLLC.PMF PLL xn ERM PLLC.LCK pll_lock ERMC.INPH fXTAL ERMC.EOM n fXTAL f0 to f4 = 0 n/m fXTAL n/m fXTAL n/2m fXTAL n/m fXTAL waitq SR1.CPUM=3, 7 fSYS CPU ICU DMA Mem. Ctrl. nWAIT 1 & fBUS ROM Flash RAM SR1.CPUM=0, 2 1 of 128 IOC.IOP n/m fXTAL 1/m SR1.CPUM=3, 7 stpclk & SR1.CPUM=0, 2 fIO I/O Bus fSUP f0perm 1/2 SR1.CPUM=3 VDD SR1.CPUM=2 f0 f1 Divider Chain f2 f3 f4 f17 Fig. 4-2: Clock system 4.3.1. PLL The PLL is composed of a phase comparator, a voltage-controlled oscillator (VCO), a frequency divider and an internal bypass. The phase comparator compares the input frequency fXTAL with the output frequency of the frequency divider, fREF. It outputs the voltage VP, which is proportional to the phase difference of the two input frequencies. VP controls the VCO which outputs the desired frequency. This frequency is fed back by the frequency divider to the phase comparator. The frequency divider divides the input frequency down to fREF which ideally is the same as fXTAL. The phase-locked state of the PLL is signaled by a lock signal. It is available as flag PLLC.LCK. It may be routed to the 44 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C LCK special output by selection in fields ANAU.LE and ANAU.LS (UVDD Analog Section). The block multiplies fXTAL by n = PMF+1 to achieve fSYS. PLL control register PLLC allows to set the desired value. CO0SEL.CO00, CO0SEL.CO01 2 HW Option HW Option CO0Mux0 CO0Mux1 SMX Out fXTAL HW Option Clock Out 4:1 Mux fXTAL Phase Comp. VP PMF = 0 VCO 1/1 1/1.5 1/2.5 1 CO0Q CO0 CO0 Interrupt Source n fXTAL fREF 1/(PMF+1) SMX Out is an output of the power-saving module. 1/1 1/1.5 1/2.5 CO1 CO1 Interrupt Source VP ~ f(XTAL - REF) PMF = 1..15 Fig. 4-3: PLL block diagram 4.3.2. I/O Clock Prescaler This prescaler derives the clock for the peripheral modules (the I/O clock fIO) from the system clock fSYS. It divides fSYS by an integer number m. The I/O clock control register IOC allows to set the desired value. m is recommended to be set equal to n/2. Fig. 4-4: Clock outputs diagram Signal CO0 is the output of a prescaler and a 4-to-1 multiplexer. Prescaler and input for the multiplexer are selectable by HW options (see Table 4-4). The output selection of the multiplexer is done by register CO0SEL, bits CO01 and CO00. The outputs of the prescalers are fed not only to the ports, but may also serve as interrupt source. The U-Ports assigned to function as clock outputs (see Table 4-4) have to be configured as SPECIAL OUT. The interrupt source output of this module is routed to the interrupt controller logic. But this does not necessarily select it as input to the interrupt controller. Check section "Interrupt Controller" for the actually selectable sources and how to select them. CO0 and CO1 are not affected by SLOW mode. Table 4-4: HW options and ports Signal HW Options Item CO0 CO0 Prescaler CO0Mux0 CO0Mux1 CO1 CO1 Prescaler Clock Out CO01C CO1C Address CO00C Initialization Item CO0 output CO0Q output CO1 output Setting U1.6, U3.3 or U7.7 special out U1.5 special out 1) U0.4, U1.5 or U7.6 special out1) 4.3.3. Divider Chain and Clock Outputs CO0 and CO1 The peripheral module divider chain receives fSYS/m and supplies the various modules with their specific clocks. Each stage of the divider chain divides its input clock by two. Thus only powers of two of the divider chain input clock are obtainable for the peripheral modules. Table 4-3 shows the effect of CPU-active mode selection on the divider output frequencies f0 through f17. Note that in modes FAST, PLL and SLOW, with n = 2m (which is recommended), f1 always equals fXTAL. Thus f1 and all further subdivided clocks are unaffected by switching between these modes. Section "HW Options" gives details about HW option-controlled clocks, their selection and their activation. Note that specifying 1/1.5 and 1/2.5 prescaled clocks results in clock signals with 33% resp. 20% duty factor. Two clock output signals, CO0 and CO1, provide external visibility of internal clocks (Figure 4-4). Clocks are selected by register CO0SEL. 1) HW Options register flag PM.U15 switches between CO0Q and CO1 at U1.5 special out. Micronas Feb. 10, 2005; 6251-579-1DS 45 CDC 32xxG-C 4.4. Memory Controller The memory controller connects the CPU to the complex memory system. It controls the various types of access and wait states. Features - support of one synchronous and up to three different asynchronous memory areas - different wait state values for sequential and nonsequential accesses to asynchronous memory - allows 8, 16 and 32-bit memory accesses from CPU - supports access to 8, 16 and 32-bit wide memory - allows big or little endian memory access. fSYS fIO Addr CR.MAP SR1.CPUM=3, 7 PATCHACC ICUACC DMAACC CR.ENDIAN CR.PSA Memory Controller Mux DATA SHEET SWS NWS WSR WS Counter 4.4.1. Principle of Operation 4.4.1.1. General The memory controller contains a memory mapping unit (MMU) to control the mapping of the whole memory system, a wait state register (WSR) to initialize the various wait states, a final state machine and a wait state counter to control the various types of access and wait states. 4.4.1.2. Initialization After reset, the CPU runs in FAST mode, the wait state counter is disabled due to SR1.CPUM=1 and no wait states for access to asynchronous memory are programmed. The access to the synchronous memory (I/O) works right after reset, independent from any setting by software. Endian mode is set by the control word via bit CR.ENDIAN. First, initialize the wait state register WSR (cf. Table 4-6). Then the PLL or PLL2 mode may be enabled, if desired. Don't change the wait state register while in PLL mode, this may lead to a memory access with undetermined wait state count in the following cycle. 4.4.1.3. Operation With proper SW initialization, the memory controller is also ready to access the asynchronous memory systems (ROM/ Flash, RAM, Boot ROM). The MMU decides from the address and the CR setting, which area in memory space contains a 8, 16 or 32-bit memory system. It preselects the different types of memory (ROM/Flash, RAM, Boot ROM and I/O-Pages) and computes the address for ROM/Flash minus 200000hex, if ROM/ Flash should be mapped to base address 200000hex. In presence of a patch module, the PATCHACC signal from the patch module signals to the MMU that the next access will be an access to the patch module instead to normal ROM/Flash. The DMAACC signal from the DMA Module signals that the next address value will be driven by DMA and not by CPU. Due to the fact that DMA always reads/writes a location in ROM/Flash, RAM or Boot ROM and writes/reads to a location in the I/O area within the same bus cycle, the MMU also preselects the I/O area, and the Memory Controller times the whole DMA cycle to the restrictions of the slow synchronous I/O area. predecrom predecram predecboot predecio waitq Bridge CPU Bus Bridge Bridge I/O ROM Boot Emu Flash Fig. 4-5: Memory controller block diagram 4.4.1.4. Inactivation Returning the memory controller to FAST mode (SR1.CPUM = 1) will immediately switch the CPU to FAST mode and change any further access to asynchronous memory to non-wait-state operation. 46 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 4.5. EMI Reduction Module (ERM) The IC contains an EMI reduction module (ERM), which is capable of reducing electromagnetic radiation that might cause interference to other electronic equipment. The concept of this circuit uses precisely defined time offsets of the master clock phases as generated by the PLL. Thus, the module is only available in PLL modes. All internal clock signals except fXTAL are affected. Thus also the sampling time points of clocked inputs and outputs of all internal modules are modulated. To avoid a possible performance degradation of, e.g., communication modules in a user environment, the maximum possible delay of the sampling clock phase can be controlled with the parameters given in table 4-6. In critical applications, I/O sampling time point modulation and EMI reduction can thus be compromised. Section 4.7. gives application hints. Features - Strong suppression of electromagnetic radiation - Precisely controlled effect on sampling time points of clocked I/O (ADC, CAN, UART, SPI etc.) - All parameters fully controllable and reproducible - Three operation modes for different purposes - Works for clock frequencies of up to 48 MHz - No degradation of CPU performance 4.5.2. Rules for Setting Parameters Each fSYS multiplier n and each mode requires its own set of parameters. For individual settings other than those given in Table 4-6 the rules are given below. For mode 1 the limits are: - The suppression strength has no effect and should be kept at 0. - The clock tolerance must not exceed the values given in the columns for strong settings. For modes 2 and 3 the limits are: - Numbers must not exceed the values given in the columns for strong settings. - The clock tolerance must be equal to or less than (suppression strength + 1) / 2. - In mode 2 the suppression strength must not exceed 43. - In mode 3 the sum of clock tolerance and suppression strength must not exceed 43. 4.5.3. Initialization For operation of the ERM, the clock system has to be in one of the PLL modes. After Reset, the ERM is in mode 0. All internal registers are reset to their default values. Registers TOL, SUP and EOM are also reset by PLLC.PMF = 0. The initialization must be done in the following order: 1. Set the clock tolerance (ERMC.TOL) to 1. Set the suppression strength (ERMC.SUP) to 1 (modes 2 and 3 only). 2. Select the desired mode (1...3) in ERMC.EOM according to Table 4-6 (steps 1. and 2. must not be done in one operation). 3. Select the desired suppression strength (ERMC.SUP). 4. Select the desired clock tolerance (ERMC.TOL). 4.5.1. Modes The ERM has four modes of operation: - Mode 0, ERM off. - Mode 1 is intended for the low fSYS frequencies of 8 MHz or 10 MHz with a clock multiplier of n = 2 (PLLC.PMF = 1). Mode 1 with a clock tolerance of 7 has a similar harmonics suppression as the formerly used EMI Reduction Module V3.1. - Mode 2. This mode is primarily intended for the deactivation process of mode 3 but may also be used for operation. It performs best at high clock frequencies. - Mode 3 gives best results at medium and high fSYS frequencies. At medium frequencies it is even capable of a certain suppression of the fundamental. In each of the three operation modes the parameters may be particularly chosen with the help of registers ERMC.SUP and ERMC.TOL, to achieve an optimum suppression while keeping phase modulation of fIO as low as possible. In Table 4-6, three sets of parameters with maximum fIO sampling delays of: - 7.5 ns (weak), - 12.5 ns (normal) and - 20 ns (strong) are given as examples. However, other individual settings are possible (see section 4.5.2.). At fSYS frequencies of 40 MHz and above only a limited EMI suppression is possible. At an fSYS of 50 MHz the ERM must be switched off (mode 0). 4.5.4. Deactivation To deactivate the ERM, the following sequence must be observed: 1. If in mode 3, enter mode 2 by writing 2 to field ERMC.EOM. 2. Set the clock tolerance parameter (ERMC.TOL) to 1 (steps 1. and 2. must not be done in one operation). 3. Set the suppression strength (ERMC.SUP) to 1 (modes 2 and 3 only). 4. Wait at least 8 fSYS cycles (e.g. CPU NOPs) before checking the in-phase flag ERMC.INPH. 5. Wait for flag ERMC.INPH to be set (may take up to 80 fSYS cycles), then clear the field ERMC.EOM to return to mode 0. This will turn off the ERM. 6. To reset the ERM, set SUP = TOL = 0 (same result achieved by setting PLLC.PMF = 0 when back in FAST mode). Micronas Feb. 10, 2005; 6251-579-1DS 47 CDC 32xxG-C 4.6. Registers DATA SHEET PLLC 7 r/w ACT x PLL Control 6 LCK x IOC 3 2 PMF 0 0 0 0 Res I/O Control 7 6 x x 5 PLLM x 4 x x 1 0 w 5 x x 4 x x 3 x x 2 1 IOP 0 x x 0 0 0 Res ACT r1: r0: LCK r1: r0: PLLM r1: r0: PMF w0: w15-1: PLL Active PLL started (PMF > 0) PLL not activated (PMF = 0) PLL Locked PLL locked PLL not locked PLL Mode Acknowledge The clock chain has switched to PLL mode Not PLL mode PLL Multiplication Factor (Table 4-6) PLL is switched off and internally bypassed. This is the standby mode for the PLL. Starts PLL with the corresponding frequency. If not active anyway, the VREFINT Generator and BVDD Regulator are enabled PMF is a write only field. Don't modify PMF in PLL mode. f SYS = n f XTAL = ( PMF + 1 ) f XTAL Above formula relates to PLL mode. IOP w I/O Clock Prescaler (Table 4-6) IOP is a write only field. f SYS f SYS PMF + 1 f 0 = ---------- = ------------------ = -------------------- f XTAL IOP + 1 m IOP + 1 Above formula relates to PLL mode. WSR 7 w Wait State Register 6 NWS 0x00 5 4 3 2 SWS 1 0 Res NWS w: SWS w: Nonsequential Wait State Bits Number of wait states at nonsequential memory access. Sequential Wait State Bits Number of wait states at sequential access. The WSR influences access to ROM, Flash and Boot ROM. ERMC 7 r/w r/w r/w r/w x EOM INPH x x ERM Control 6 5 4 TSEL x x x x SUP 0x00000000 x x TOL x x CO0SEL 3 2 1 0 3 2 1 0 Res w Clock Out 0 Selection 6 x x 7 x x 5 x x 4 x x 3 x x 2 x x 1 CO01 0 0 CO00 0 Res CO00, CO01 Clock Out Bit 0 and 1 w: Clock selection Table 4-5: CO00 and CO01 Usage CO01 0 0 1 1 CO00 0 1 0 1 Selection CO0Mux0 CO0Mux1 SMX Out (Power Saving Module) fXTAL TSEL r/w EOM r/w3: r/w2: r/w1: r/w0: TOL r/w15-0: INPH r1: r0: SUP r/w63-0 Test Select Factory use only. ERM Operation Mode Mode 3 Mode 2 Mode 1 Off Clock Tolerance (see Table 4-6 and 4-7) In Phase (during deactivation) Phase is 0 or 1 Phase > 1 Suppression Strength (see Table 4-6 and 4-7) 48 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 4.6.1. Recommended Settings Tables 4-6 and 4-7 list settings available for the EMU device. When emulating a specific target device (MCM or mask ROM), use the recommended settings of that device only. Settings differing from these two lists shall not be used and may result in undefined behavior. It is required not to operate I/O faster than Flash. Suppression Strength (SUP) and Clock Tolerance (TOL) may be varied between zero and the values for strong settings according to the rules in Section 4.5.2. The given limits must not be exceeded Table 4-6: PLL and ERM modes: Recommended settings and resulting operating frequencies (MHz) fXTAL CPU Program Storage PLLC. PMF 1 3 fBUS 8 16 8 24 5 24 12 8 32 7 16 10.7 40 9 20 13.3 10 48 11 24 16 12 5 10 20 1 3 10 20 10 30 5 15 10 40 7 20 13.3 10 50 9 25 16.7 12.5 WSR 0x00 0x00 0x11 0x00 0x11 0x22 0x11 0x22 0x11 0x22 0x33 0x11 0x22 0x33 0x00 0x00 0x11 0x11 0x22 0x11 0x22 0x33 0x11 0x22 0x33 4 3 2 10 0 1 5 4 3 2 I/O ERMC.EOM = 1 Weak SUP TOL fSYS 4 8 16 fIO= f0 8 IOC. IOP 0 1 Normal SUP TOL Strong SUP TOL ERMC.EOM = 2 or 3 Weak SUP TOL Normal SUP TOL Strong SUP 11 22 22 33 31 31 31 31 37 37 37 42 42 42 14 28 28 31 31 37 37 37 TOL 6 11 11 1 12 12 12 12 6 6 6 1 1 1 7 6 12 12 12 6 6 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 8 8 2 12 12 12 12 6 6 6 1 1 1 5 10 10 14 14 6 6 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 14 14 2 15 15 12 12 6 6 6 1 1 1 8 13 15 14 14 6 6 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 15 15 2 15 15 12 12 6 6 6 1 1 1 14 13 15 14 14 6 6 6 4 8 8 12 12 12 16 16 21 21 21 25 25 25 5 10 10 15 15 21 21 21 2 4 4 1 6 6 8 8 6 6 6 1 1 1 3 5 5 8 8 6 6 6 7 14 14 21 21 21 28 28 35 35 35 42 42 42 8 17 17 26 26 35 35 35 4 7 7 1 11 11 12 12 6 6 6 1 1 1 4 6 9 12 12 6 6 6 set ERMC.EOM = 0 set ERMC.EOM = 0 Micronas Feb. 10, 2005; 6251-579-1DS 49 CDC 32xxG-C DATA SHEET Table 4-7: PLL2 and ERM Modes: Settings sacrificing unlimited operation of peripheral modules and resulting operating frequencies (MHz) fXTAL CPU Flash I/O ERMC.EOM = 1 Weak SUP TOL fSYS 4 12 PLLC. PMF 2 fBUS 6 12 20 5 15 4 2 10 7.5 WSR 0x11 0x00 0x11 0x11 5 4 2 fIO= f0 4 IOC. IOP 2 Normal SUP TOL Strong SUP TOL ERMC.EOM = 2 or 3 Weak SUP TOL Normal SUP TOL Strong SUP 16 16 28 21 TOL 8 2 8 11 0 0 0 0 6 5 10 7 0 0 0 0 10 5 15 13 0 0 0 0 15 5 15 15 6 6 10 7 3 2 5 4 10 10 17 13 5 2 8 7 4.7. PLL/ERM Application Notes 4.7.1. PLL Jitter The embedded PLL synchronizes every n-th fSYS cycle to the externally applied fXTAL signal. This synchronization smoothly tries to cancel out influences from power supply noise and fXTAL fluctuations. Depending on the application, this permanent re-synchronization process is expected to introduce some nanoseconds of phase jitter to fIO. It is important to note that PLL jitter does not introduce a noticeable frequency error, because the phase stays locked to the fXTAL reference and fluctuates, even over long times, only within the same tight limits. Even with a PLL induced fIO jitter of 5 ns, the maximum observable frequency error between two fIO clocks - spaced 1s apart is (1 s 2 x 5 ns) / 1 s = 1%, - spaced 1ms apart is (1 ms 2 x 5ns) / 1 ms = 10 ppm, - spaced 1s apart is (1 s 2 x 5 ns) / 1 s = 0.01 ppm, and so forth. offset between transmitting and receiving station, that can be tolerated without transmission error. Viewed from the receiving station, a frequency offset of the transmitting station is tolerable, as long as over the length of a complete telegram, every bit can still be detected unambiguously. Once the tolerable frequency offset is exceeded, communication is fatally disturbed. This tolerable offset is dependent on the capability of the involved circuitry to detect and compensate for frequency offset. In the further discussion, the clock tolerance TOL is defined as percentage offset of the actual from the nominal frequency f act - f nom TOL = -------------------------f nom Note that each transmitting and receiving station are allowed this same tolerance from nominal: ftrans=fnomTOL and frec=fnomTOL The resulting maximum offset between transmitter and receiver is thus 2 x TOL. 4.7.3.1. UART Let us consider the tolerable frequency offset in the case of the UART. The baud rate frequency is always the sample clock frequency, divided by 8. The maximum telegram length is 12 bit. A transmitter frequency offset is tolerable as long as 12 x 8 3 receiver sample clocks equal 12 x 8 transmitter sample clocks, which gives a transmitter frequency of fTrans = fRec(12 x8 / (12 x 8 3)) = fRec 3.23% and TOL = 1.61%. PLL and ERM jitter claim a certain portion of this tolerable offset. The assumption is that both influences add up to 15 ns of fIO jitter, and that fIO = f0 = 8 MHz. With the baud rate set to 500 kBd, fSAMPLE equals 4 MHz. With this setting, PLL and ERM jitter consume 2 x 15 ns / 750 ns = 4% of the tolerable transmitter frequency offset and reduce TOL to 1.55%. 4.7.2. ERM "Jitter" The effect of the ERM on fIO phase and frequency is similar to that of PLL jitter in that it adds limited phase modulation. However, this ERM-induced jitter is especially tailored to improve the electromagnetic emission properties of the device. Section 4.5.1. gives details on setting the maximum phase delay: - 7.5 ns (weak) translates to 3.75 ns of fIO jitter, - 12.5 ns (normal) translates to 6.25 ns of fIO jitter, - 20 ns (strong) translates to 10 ns of fIO jitter. From these figures it is evident, that ERM introduces a jitter that, in its extent, is comparable to PLL jitter. Both influences may be added to estimate the combined PLL/ERM effect on I/O module operation. 4.7.3. Influence of PLL/ERM on Module Operation DIGITbus, SPI and I2C synchronize external devices to one master clock. Their operation is hardly impeded by PLL/ERM jitter. Modules such as UART and CAN communicate with external fixed-frequency devices, and there is a maximum frequency 50 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Example (f0 = 8MHz) With the baud rate set to 1 MBd, tBit equals 1 s and is divided into 8 time quants (tQ = 125 ns). tSJW and tTSEG2 are programmed to 2 tQ (= tPhase Seg1 = tPhase Seg2). 3 tQ are reserved for the propagation delay segment. In the first case the maximum tolerance TOL is 1.25% (edge to edge): 2TOL ----------------------- = 0,0125 2 x 10 x 8 In the second case, TOL is 0.98% (edge to sample point): 2 TOL ------------------------------------- = 0,0098 2 x ( 13 x 8 - 2 ) The smaller value of the above (0.98%) is relevant. Following the UART example, PLL/ERM jitter consumes up to 2 x 15 ns of 250 ns (SJW = 2 time quants). This gives 30 ns / 250 ns = 12% of this tolerance, thus reducing TOL to 0.86%. With the baud rate set to 500 kBd, tBit = 2 s and tQ = 250 ns. The maximum tolerance TOL of 0.98% is reduced by 2 x 15 ns / 500 ns = 6.0% to 0.92%. 4.7.3.3. DIGITbus The DIGITbus master synchronizes with external devices via the serial data line. The slave node recovers the transmission clock from the data signal via an own PLL. This PLL will lock to the long-term average frequency of the master, and the slave node sees PLL/ERM jitter as a short-term frequency offset. Following the UART example, one can define the tolerable frequency offset: Every bit starts with a rising edge and thus every bit has a resynchronization point. The bit period (tBit) is divided into four equal-length parts. Falling edges happen nominally after 1/4, 2/4 or 3/4 of the bit period. After 4/4 of the bit period a rising edge indicates the beginning of the next bit. The DIGITbus logic tolerates a jitter of these edges up to 1/8 of the bit period. Thus, a transmitter frequency offset is tolerable up to fTrans = fRec(1 1/8) = fRec 12.5% and TOL = 6.25%. Again following the UART example, ERM/PLL jitter influences this tolerable offset: With the baud rate set to 31.25 kBd, 1/8 of the bit period is 4 s. PLL/ERM jitter reduces the maximum tolerance TOL of 6.25% by 2 x 15 ns / 4s = 0.75% to 6.2%. 4.7.3.4. SPI and I2C Modules like SPI and I2C synchronize with external devices by the serial clock. Thus, no frequency offset between transmitting and receiving station can develop, and no adverse effects of PLL/ERM operation are expected. With the baud rate set to 19.23 kBd, fSAMPLE equals 153.84 kHz. With this setting, PLL and ERM jitter consume 2 x 15 ns / 19.5 s = 0.15% of the tolerable transmitter frequency offset and reduce TOL only slightly, to 1.605%. 4.7.3.2. CAN The CAN module contains logic that re-synchronizes a receiver to a transmitter several times during a telegram. By these means, a receiver is able to adapt to the transmitter frequency within narrow limits. Two situations have to be distinguished: 1. Bit stuffing guarantees a maximum of 10 bit periods between two consecutive re-synchronization edges. Therefore the accumulated phase error must be less than the programmed re-synchronization jump width (SJW). The limitation that this situation imposes on the maximum TOL can be expressed as: t SJW 2 x TOL ------------------10 x t Bit or t SJW TOL ---------------------------2 x 10 x t Bit 2. Another limit on the maximum TOL is set by the situation where the CAN logic must be able to correctly sample the first bit after an error frame. This is the 13th bit after the last re-synchronization. This limitation can be expressed as: min ( t Phase Seg1, t Phase Seg2 ) 2 x TOL --------------------------------------------------------------13 x t Bit - t Phase Seg2 or min ( t Phase Seg1, t Phase Seg2 ) TOL --------------------------------------------------------------2 x ( 13 x t Bit - t Phase Seg2 ) Example (f0 = 10MHz) With the baud rate set to 1 MBd, tBit equals 1 s and is divided into 10 time quants (tQ = 100ns). tSJW and tTSEG2 are programmed to 3 tQ (= tPhase Seg1 = tPhase Seg2). 3 tQ are reserved for the propagation delay segment. In the first case the maximum tolerance TOL is 1.5% (edge to edge): 3 TOL -------------------------- = 0,015 2 x 10 x 10 In the second case, TOL is 1.2% (edge to sample point): 3 TOL ---------------------------------------- = 0,012 2 x ( 13 x 10 - 3 ) The smaller value of the above (1.2%) is relevant. Following the UART example, PLL/ERM jitter consumes up to 2 x 15 ns of 300 ns (SJW = 3 time quants). This makes 30 ns / 300 ns = 10% of this tolerance, thus reducing TOL to 1.08%. With the baud rate set to 500 kBd, tBit = 2 s and tQ = 200 ns, the maximum tolerance TOL of 1.2% is reduced by 2 x 15 ns / 600 ns = 5% to 1.14%. Micronas Feb. 10, 2005; 6251-579-1DS 51 CDC 32xxG-C DATA SHEET 52 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 5. Memory and Special Function ROM (SFR) System address range (16M) 00FF.FFFF CR.MAP = 00 RESETQ = 1 CR.MAP = 01 CR.MAP = 1x RESETQ = 0 TEST2-Pin = 0 TEST2-Pin = 1 .5M F8.0000 I/O I/O I/O F0.0000 .5M rsvd debug SFROM SFROM SFROM E0.0000 2M RAM C0.0000 RAM RAM A0.0000 8M ROM/Flash ROM/Flash 20.0000 2M RAM 0 ROM/Flash ROM/Flash SFROM SFROM Fig. 5-1: Address map. Most common settings Micronas Feb. 10, 2005; 6251-579-1DS 53 CDC 32xxG-C 5.1. RAM and ROM On-chip RAM is composed of static RAM cells. It is protected against disturbances during reset as long as the specified operating voltages are available. The 128PQFP multichip module also contains a 512 KB Flash EEPROM of the AMD Am29LV400BT type (top boot configuration). This device exhibits electrical byte program and sector erase functions. Refer to the AMD data sheet for details. Future mask ROM derivatives may be specified to contain less or more internal RAM and ROM than this IC: - ROM will grow upward from 0x0200000 to 0x09FFFFF (8 MByte) and can be remapped to physical address 0 (growing upward to 0x07FFFFF). It is 16 bit wide and is asynchronously accessed with wait states. - RAM will always grow upward from physical address 0x0C00000 to 0x0DFFFFF (2 MByte) and can be mirrored to physical address 0. It is 32 bit wide and is asynchronously accessed without wait states. - SFR will grow upward from physical address 0x0F00000 to 0x0F7FFFF (0.5 MByte) and can be mirrored to physical address 0. - The I/O area will grow upward from physical address 0x0F80000 to 0x0FFFFFF (0.5 MByte). It is 16 bit wide and is asynchronously accessed with wait states. Mirrored means the memory is accessible at both locations. Remapped means the memory is accessible at the new location only. All parts (ROM, Flash and EMU) contain at least the I/O area, the RAM and the SFR. DATA SHEET Table 5-1: Reserved addresses Address Size [byte] Usage if mapped/mirrored to 0 RAM 030 - 5F 02C - 2F 02A - 2B 028 - 29 024 - 27 020 - 23 01C - 1F 018 - 1B 014 - 17 010 - 13 00C - 0F 008 - 0B 004 - 07 000 - 03 48 4 2 2 4 4 4 4 4 4 4 4 4 4 Generalpurpose RAM. No HWdefined action. ROM/ Flash HW options Factory ID reserved ROM ID Security Vector Control word FIQ (Fast Interrupt) IRQ (Interrupt) Reserved Data Abort Prefetch Abort SWI (Software Interrupt) Undefined instruction Reset ARM ID SFR 5.1.1. Reserved Addresses Reserved addresses (Table 5-1) are memory locations which define the behavior of internal HW or external systems. In our system the memory locations at address 0 and following have dedicated functions. The function of these memory locations depend on which kind of physical memory is mapped to these locations. As you can see in Fig. 5-1, ROM/Flash or SFR is mapped to location 0 at reset. Thus, a meaningful control word and reset vector can be obtained at start-up. 5.1.1.1. HW Options Please refer to section "Hardware Options" for information on the layout of the HW options field and the corresponding registers in the I/O area. To activate the HW-option-related functions, the SW has to copy them to the corresponding locations in the I/O area. But nevertheless these are HW options. It is not possible to modify them by SW in future ROM parts. 5.1.1.2. ROM ID The ROM ID serves as identification of the corresponding application/SFR program. It will be read by an external system (test, debug) and does not influence internal HW. The ROM ID contains a half-word sized hexadecimal value. The range is 0x0000 to 0xFFFF. 5.1.1.3. Factory ID The factory ID contains a factory-defined code. It holds information about the HW version and other items. It can be read by an external system (test, debug) and does not influence internal HW. The SFR system may use this information and adapt its behavior according to the factory ID. The layout of the factory ID is not yet defined. 5.1.1.4. Security Vector (SV) If the security vector is set (equal to 0x55AA55AA), the SFR does not enable the JTAG interface. In this way the application program may keep the JTAG access disabled. An empty (erased) Flash ROM contains all ones. Hence the JTAG access is enabled. Keep to the following sequence to reprogram a Flash ROM: 1. Clear the SV (i.e., program the SV address with 0x00000000 or any other value different from 0x55AA55AA). 2. Erase the Flash ROM (this sets the SV to 0xFFFFFFFF). 3. Program all of the Flash ROM, but skip the SV address (leave it at 0x0xFFFFFFFF). 4. Verify the Flash ROM. 5. If ok, set the SV (write 0x55AA55AA to the SV address). Otherwise return to step 2. This procedure guarantees that the JTAG interface will be enabled after reset via SFR, if something has gone wrong during Flash ROM programming. 54 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C allows the identification of the implemented processor. No CP15 has been implemented so far, but the ARM ID field may contain the same information. 5.1.1.6. Control Word The control word defines the behavior of the HW during reset. Refer to section "Core Logic" for information on control word definition. A correct application program should provide a separate way and interface to enable JTAG and to modify the Security Vector. To allow easy JTAG access during development and debugging, leave the SV not set. 5.1.1.5. ARM ID The ARM core can comprise a system control coprocessor (CP15), which contains among other things an ID Register. It 5.2. I/O Map The I/O region (Table 5-2) is divided into the lower part (addresses 00F80000 to 0x00FBFFFF) which is connected to the 8 bit wide bus and into the upper part (addresses 00FC0000 to 0x00FFFFFF) which is connected to the 32-bitwide bus. Please refer to section "Register Cross Reference Table" for detailed I/O register mapping. Access to I/O modules which are connected to the 8-bit-wide bus is restricted: If not otherwise mentioned those modules must be accessed by byte access only. This memory area is organized in little endian format. If the CPU operates in big endian format, only byte access is recommended. Table 5-2: I/O map Address Size [byte] Access 32-bit, asynchronous, no wait states Register IRQ and FIQ registers DMA registers Core registers Free 8-bit, synchronous, wait states Free Registers Free CAN registers CAN-RAM 00FFFFFF 256 00FFFF00 00FFFEFF 256 00FFFE00 00FFFDFF 512 00FFFC00 00FFFBFF 255 k 00FC0000 00FBFFFF 190 k 00F90800 00F907FF 2 k 00F90000 00F8FFFF 59.5 k 00F81200 00F811FF 512 00F81000 00F80FFF 4 k 00F80000 Micronas Feb. 10, 2005; 6251-579-1DS 55 CDC 32xxG-C 5.3. Special Function ROM (SFR) The job of the SFR is to enable the JTAG interface if necessary. Further actions as there are download, Flash ROM programming or debugging and monitoring have to be done via JTAG interface. If TEST2 pin is held high during reset, the control word from the SFR is copied to the control register by HW. The SFR control word is configured to start program execution from the SFR, mirrored to location 0. The SFR control word disables JTAG. DATA SHEET the selected function if, what and how additional pins will be used for further operations. For notifications UART0 is used with 9600 Bd, 8 data bits, 2 stop bits, no parity and no kind of handshake: - P0[1:0] = 0: Erase Flash: A blank check of the Flash ROM is executed to detect if it is erased. If the Flash ROM is not clear, it is erased and checked again, until detected as completely blank. When finished, "Flash is blank" is indicated via UART 0. - P0[1:0] = 1: Run Test Program: For test purposes an endless program sequence is executed, using most parts of the chip internal modules. Make sure to run this program in the test environment only! - P0[1:0] = 2: Check IDs: ROM and Factory ID are read out of the Flash ROM and indicated via UART 0. In addition to the 16-bit ROM ID (RID) the adjacent reserved 2 bytes are displayed as upper half word of the RID, e.g.: "RID: 0x0x56BC78AB FID: 0xDE9ACDFE" - P0[1:0] = 3: Generate Checksum: A 32-bit check sum of the whole Flash ROM content is generated by summing up all data words, without considering carry-overs. The result is shown as hex value via UART 0, e.g.: "CHECKSUM: 0x3456BCDE". The watchdog is not triggered in the SFR program. Especially when the program is in the endless loop this would cause problems. But this endless loop will not be reached in ROM parts as long as the security vector is valid. 5.3.1. Principle of operation The first instruction of the SFR (the reset vector) loads the address of the next instruction in the original SFR (0xF00100, above the SFR HW options) into the program counter. This causes a jump from the mirrored SFR to the original SFR. The remaining part of the program is running in the original SFR and remapping of the memory does not influence correct operation of the SFR program. If the TEST pin is detected low immediately after the SFR Firmware is started, the security vector in the Flash ROM is checked (Table 5-3). If the security vector is set in the application program, the application is started, otherwise the JTAG interface is enabled and the program stays in an endless loop to allow TAP access. If the TEST pin is detected high immediately after the SFR firmware is started, additional functions may be invoked, selected by the digital levels at the analog input pins P0[1:0] (Table 5-3). This mode is not intended to be used within the application environment but for test purposes only! It depends on Table 5-3: Startup control by TEST pin and security vector (SV), TEST2 pin = 1 TEST pin 0 0 1 SV set not set x QFP 128 Use application CW in flash to start the application in flash Enable application JTAG to allow debugging Decode further input selection to - run Test Program - erase Flash 1) - generate checksum - indicate IDs EMU Use application CW in emulation memory to start the application in emulation memory 1) Inadvertent execution of critical code additionally blocked by HW decoding of TEST pin state. 56 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Start of SF ROM Routine Jump to 0xF00100 P0[1:0] = 0 = No Erase Flash ? TEST pin low ? Yes EWE = 1 Yes Erase Flash Flash blank ? Security Vector set ? No Yes Yes No CR = CW/FLASH MFPL = 0 CR.JTAG = 1 indicate Flash blank No Jump to 0x0 Endless loop P0[1:0] = 3 = generate checksum ? Yes generate and indicate checksum EWE = 1 MFPL = 0 CR.JTAG = 1 No Endless loop Endless loop P0[1:0] = 2 = check IDs ? Yes indicate IDs No Endless loop Security Vector set ? No Yes EWE = 1 MFPL = 0 CR.JTAG = 1 P0[1:0] = 1 = run Test program Fig. 5-2: Flow chart of special-function ROM routine Micronas Feb. 10, 2005; 6251-579-1DS 57 CDC 32xxG-C DATA SHEET 58 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 6. Core Logic 6.1. Control Word (CW) A number of important system configuration properties are selectable during device start-up by means of a unique control word (CW). As can be seen from Table 6-1, the device disables external access (through the Multifunction port) to internal code, as long as MFPLR.MFPL is 1 (= state after UVDD power-up). Setting it to 0 requires internal SW. By this means, an effective device lock mechanism is implemented that prevents unauthorized access to internal SW. See section 6.2. on the device lock module (DLM) for details. In ROM parts, flag MFPLR.MFPL is available, but does not lock the multifunction port, so Table 6-1 reduces to Table 6- 2. Table 6-2: CW fetch in ROM parts (QFP128) "Control Word Fetch" desired from Necessary reset config. of pins TEST2 Internal ROM External via Multifunction port Int. Special-Function ROM 0 1 1 0 0 1 TEST 0 1 x 6.1.1. Reset Active At the end of the reset period, the device fetches this CW from address locations 0x20 to 0x23 of a source that is determined by the state of pins TEST and TEST2 and flag MFPLR.MFPL, see Table 6-1 for MCM and EMU parts, Table 6-2 for ROM parts. Table 6-1: CW fetch in MCM parts (QFP128), and in EMU parts (CPGA257) MCM EMU Necessary reset configuration TEST2 0 TEST 0 MFPL x "Control Word Fetch" desired from Int. Flash Int. Flash Ext. via EMU port Ext. via EMU port 6.1.2. Reset Inactive 0 1 x x 1) Ext. via multifunction port Int. special-function ROM 1) When exiting reset, the CW is read and stored in the control register (CR) and the system will start up according to the configuration defined therein. Normally the CW is fetched from the same memory that the system will start executing code from. Table 6-3 gives fixed CWs for a list of the most commonly used configurations. Only available after a non-power-on RESET with MFPL = 0 set before Table 6-3: Some common system configurations and the corresponding CW setting Part type EMU "Program Start" desired from Additional desired properties Necessary CW 31:16 ext. 32-bit sync SRAM (e.g. MT55L256L32F) on EMU port Trace Bus ETM mode 16-bit ROM/Flash emulation, Trace Bus ETM mode 16-bit ROM/Flash emulation, Trace Bus Analyzer mode, Appl. JTAG released ext. 32-bit async auto-power-down Flash (2x Am29LV400BT) on EMU port ext. 16-bit async. auto-power-down Flash (Am29LV400BT) on EMU port MCM ROM int. 16-bit Flash (Am29LV400BT) int. 16-bit ROM Trace Bus Analyzer mode Trace Bus ETM mode 0xFFBA 0xFFBB 0xFFBB 15:0 0x835F 0x835F 0xA3DF 0xFFBA Don't care Don't care Don't care Don't care 0x675F 0x2F5F 0x4F5F 0x7F5F 0x7F5F Micronas Feb. 10, 2005; 6251-579-1DS 59 CDC 32xxG-C For special purposes, the CW source and the program source may differ. For these purposes, a detailed description DATA SHEET of the CW and CR function is given in the chapter "Control Register and Memory Interface". 6.2. Device Lock Module (DLM) Together with the corresponding application software, the DLM allows to establish protections against unwanted device accesses from outside the device and against unwanted flash data erase. It is composed of the - multifunction port lock (MFPL), the - EMU bus write enable control bit CR.EWE and the - special-function ROM (SFR) system. Appropriate precautions within the application software are necessary, especially controlling DMA and PATCH activities, not to undermine a system lock. 6.2.3. Special Function ROM (SFR) To get the CW from the multifunction port, MFPL has to be set to 0 before. This can be achieved either by a run through an appropriate part of the special-function ROM code or by a corresponding application software that prepares MFPL = 0. The necessary RESET to follow must not be a POR, because it resets MFPL to 1. Power-saving modes also set MFPL = 1. For details on the SFR please refer to chapter "Memory and Special-Function ROM (SFR) System". 6.2.1. Multifunction Port Lock (MFPL) To protect the memories contents against access from outside the device, the multifunction port, used as test bus, has to have a protection mechanism that is active by default. Together with appropriate hardware, the multifunction port lock (MFPL), controlled by a bit located in the multifunction port lock register (MFPLR), ensures a disabled multifunction port after POR (Power On RESET). MFPLR 7 r/w x x Multifunction Port Lock Register 6 x x 5 x x 4 x x 3 x x 2 x x 1 x x 0 MFPL 11) Res 1) Set by POR or wake-up from power-saving modes. Multifunction Port Lock Locked Not locked MFPL r/w1: r/w0: 6.2.2. Emu Bus Write Enable (EWE) In addition to MFPL, which protects the device memories against accesses from outside, with EMU bus write enable (EWE) inactive, the EMU bus is protected against write from anywhere, externally via test bus or internally via EMU or memory bus. EWE is controlled by a bit in the control register which is cleared (inactive) by RESET. It prevents unauthorized and unintended Flash write and/or erase. EWE is located in the CR to be set easily by the control word generation of the emulation hardware. Code can be downloaded into the emulation RAM without having to enter a dedicated register write command or running a script file before. Write accesses by the debugger, e.g. to set break points, may take place immediately after RESET. For details on the control register, please refer to chapter "Control Register and Memory Interface". With MFPL and CR.JTAG the device can be protected against external read and write accesses. In addition, CR.EWE offers locking the Emu Bus/Flash memory separately against external and internal write and erase. With the reset status of EWE = 0 no Flash write is possible at first. EWE = 1 has to be programmed by software before. 60 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 6.3. Standby Registers The standby registers SR0 to SR1 allow the user to switch on/off power or clock supply of single modules. With these flags it is possible to greatly influence power consumption and its related electromagnetic interference. For details on enabling and disabling procedures and the standby state, please refer to the specific module descriptions. PSLW r/w1: r/w0: UART0 r/w1: r/w0: ADC r/w1: r/w0: TIM1 r/w1: r/w0: XTAL r/w1: r/w0: SM r/w1: r/w0: SPI1 r/w1: r/w0: CAN0 r/w1: r/w0: CCC0 r/w1: r/w0: SPI0 r/w1: r/w0: Port Slow Mode Slow mode. Fast mode. UART 0 Module active. Module off. ADC Module Module active. Module off. Timer 1 Module active. Module off. Quartz Oscillator Mode Start-Up Mode active (default after Reset). Run Mode active. Stepper Motor Module active. Module off. SPI 1 Module active. Module off. CAN Module 0 Module active. Module off. Capture Compare Counter 0 Module active. Module off. SPI 0 Module active. Module off. SR0 7 r/w r/w r/w r/w I2C1 TIM2 LCD SM Standby Register 0 6 I2C0 TIM3 x x 5 x TIM4 PSLW x 4 x UART1 UART0 x 3 x x ADC SPI1 2 CAN3 DGB x CAN0 1 CAN2 CCC1 TIM1 CCC0 0 CAN1 x XTAL SPI0 Offs 3 2 1 0 Res 0x00000100 I2C1 r/w1: r/w0: I2C0 r/w1: r/w0: CAN3 r/w1: r/w0: CAN2 r/w1: r/w0: CAN1 r/w1: r/w0: TIM2 r/w1: r/w0: TIM3 r/w1: r/w0: TIM4 r/w1: r/w0: UART1 r/w1: r/w0: DGB r/w1: r/w0: CCC1 r/w1: r/w0: LCD r/w1: r/w0: I2C Module 1 Enabled Disabled I2C Module 0 Enabled Disabled CAN Module 3 Module active. Module off. CAN Module 2 Module active. Module off. CAN Module 1 Module active. Module off. Timer 2 Module active. Module off. Timer 3 Module active. Module off. Timer 4 Module active. Module off. UART 1 Module active. Module off. DIGITbus Master Module active. Module off. Capture Compare Counter 1 Module active. Module off. LCD Module Module active. Module off. SR1 7 r/w r/w r/w r/w x x PFM1 IRQ Standby Register 1 6 x x PFM0 FIQ 5 x x PWM11 x 4 x x PWM9 x 3 x x PWM7 x 2 x x PWM5 1 x x PWM3 CPUM 0 x x PWM1 Offs 3 2 1 0 Res 0x00000001 PFM1 r/w1: r/w0: PFM0 r/w1: r/w0: PWM11 r/w1: r/w0: PWM9 r/w1: r/w0: Pulse Frequency Modulator 1 On Off Pulse Frequency Modulator 0 On Off Pulse Width Modulator 11 On Off Pulse Width Modulator 9 On Off Micronas Feb. 10, 2005; 6251-579-1DS 61 CDC 32xxG-C PWM7 r/w1: r/w0: PWM5 r/w1: r/w0: PWM3 r/w1: r/w0: PWM1 r/w1: r/w0: Pulse Width Modulator 7 On Off Pulse Width Modulator 5 On Off Pulse Width Modulator 3 On Off Pulse Width Modulator 1 On Off IRQ r/w1: r/w0: FIQ r/w1: r/w0: IRQ Interrupt Controller Enabled Disabled FIQ Interrupt Controller Enabled Disabled DATA SHEET CPUM CPU Mode Clock selection for CPU and peripheral modules (Section "CPU and Clock System"). Change CPUM by 32-bit access only. 6.4. UVDD Analog Section 6.4.1. VBG Generator The low-power VBG generator generates bias signals which are necessary for the operation of all "UVDD analog section" modules. Furthermore, it produces a reference voltage VBG, that is delivered to the VDD and FVDD regulators, the RESET and ALARM comparators and the UVDD supply supervision. This module is permanently enabled except during powersaving modes. 6.4.2. VDD Regulator The VDD regulator generates the 2.5 V VDD supply voltage for the internal core logic from the 5 V UVDD. It derives its reference from the VBG generator. VDD must be buffered externally by a 220 nF ceramic capacitor in parallel with a 10 F tantalum capacitor. This module is permanently enabled except during powersaving modes. A certain set-up time has to elapse after power-up of UVDD for VDD to stabilize. During this time, the supply supervision (cf. 6.4.7.) generates a power-on reset. An overload condition in the regulator (current or voltage drop-out) generates an immediate reset and is stored in flag ANAU.VE. The immediate overload signal may be routed to the LCK special output by selection in field ANAU.LS. 6.4.3. VDD Auxiliary Regulator The low-power VDD auxiliary regulator generates a reduced supply voltage for the core logic from the 5 V UVDD. This module is enabled only during IDLE mode, where no clocked operation is required. 6.4.4. FVDD Regulator The FVDD regulator generates the 3.3 V FVDD supply voltage for the external Flash memory device from the 5 V UVDD. It derives its reference from the VBG generator. FVDD must be buffered externally by a 470 nF ceramic capacitor in parallel with a 3.3 F tantalum capacitor. This module is permanently enabled except during powersaving modes. A certain set-up time has to elapse after power-up of UVDD for FVDD to stabilize. During this time, the supply supervision (cf. 6.4.7.) generates a power-on reset. An overload condition in the regulator (current or voltage drop-out) generates an immediate "reset" and is stored in flag ANAU.FVE. The immediate overload signal may be routed to the LCK special output by selection in field ANAU.LS. 6.4.5. ALARM Comparator The alarm comparator on the pin RESETQ allows the detection of a threshold higher than the reset threshold. An alarm interrupt can be triggered with the output of this comparator. To obtain a result that is independent from UVDD, the level of pin RESETQ is compared to the VBG reference voltage. The comparator features a small built-in hysteresis. The output constitutes the RESETQ/ALARM interrupt source and must be enabled by setting flag ANAU.EAL. Please refer to section 6.5.1. for functional details. The interrupt source output is routed to the interrupt controller logic. But this does not necessarily select it as input to the interrupt controller. Check section "Interrupt Controller" for the actually selectable sources and how to select them. The alarm interrupt is a level triggered interrupt. The interrupt is active as long as the voltage on pin RESETQ remains between the two thresholds of the ALARM and the RESET comparator. 62 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C VBG ON_5 DBG.DISA 1 2.5V 10% en VBG Generator UVDD UVDD Logic UVSS en err + VDD Regulator 2.5V VDD VDD Logic VSS 1.2V AUXON_5 en + - VDD Auxiliary en err + FVDD Regulator 3.3V ext. Flash FVDD FVSS RESETQ en ANAU.EAL fIO ANAU.LS 2 fvdd_err vdd_err LCK MUX + ALARM Comp. & RESET/ ALARM Interrupt Source + en VREFR RESET Comp. RES_5 bvdd_err pll_lock ANAU.FVE ANAU.VE en + Supply Supervision 1 POR SR0.LCD en + + LCD Supply XTAL1 2/ 3UVDD 1/ 3UVDD VSS SR0.XTAL ON_5 OSC.XM 1 run en XTAL Oscillator XTAL2 Fig. 6-1: UVDD analog section block diagram Micronas Feb. 10, 2005; 6251-579-1DS 63 CDC 32xxG-C 6.4.6. RESET Comparator As long as the reset comparator on the pin RESETQ detects the low level, the overall IC is reset except the PSM/RTC. To obtain a result that is independent from UVDD, the level of pin RESETQ is compared to the scaled down VBG reference voltage. The comparator features a built-in hysteresis. DATA SHEET During power-saving modes, the comparator function is not available and is bypassed by a simple CMOS Schmitt input. Full CMOS input levels (Vil = UVSS 0.3 V and Vih = UVDD 0.3 V) are thus required on this input in these modes. Please refer to sections 6.5.2. and 6.5.3. for functional details. 6.4.7. Supply Supervision When UVDD drops below a level VREFPOR of approx. 2.8 V, or when the internal VDD or FVDD regulators detect an overload condition, this module generates a power-on reset signal POR that is routed to the Reset Logic. Refer to section 6.5.2.1. for more details. This module is permanently active, except during power-saving modes. 6.4.8. XTAL Oscillator The XTAL oscillator generates a 4 to 5 MHz reference signal from an external quartz resonator, cf. section "Electrical Characteristics" for quartz data. A reset sets the module to START-UP mode, where, at the expense of a higher current consumption, marginal quartzes receive more drive to ease start-up of oscillation. After start-up of the CPU program, register SR0.XTAL may be cleared by SW to set the XTAL oscillator to RUN mode, where current consumption is at its standard level. For operation at UVDD levels between 3.5 V and 4.5 V, continuous operation of the module in START-UP mode may be necessary to guarantee sufficient drive to the connected quartz. Switching between START-UP and RUN modes must not be done in CPU modes PLL or PLL2, as this might lead to unpredictable behavior of the clock system. This module is permanently active, except during power-saving modes, where continued operation may be selected for STANDBY and IDLE modes in register OSC.XM. 6.4.9. UVDD Analog Registers ANAU 7 r/w EAL 0 Analog UVDD Register 6 x 0 w2: w3: 1 FVE 0 FVDD Regulator Error. BVDD Regulator Error. LCK Enable LCK signal at pin. PFM1 output at pin. FVDD Regulator Error Flag Out of specification. Normal operation. Reset flag. No action. VDD Regulator Error Flag Out of specification. Normal operation. Reset flag. No action. 5 LS 4 3 LE 2 x - 0 VE 0 Res LE w1: w0: FVE r1: r0: w1: w0: VE r1: r0: w1: w0: 0 0 EAL r/w1: r/w0: LS w0: w1: Enable RESET/ALARM Interrupt Source output Enabled. Disabled. LCK Output Select PLL Lock Signal. VDD Regulator Error. 6.5. Reset Logic 6.5.1. Alarm Function The alarm comparator on the pin RESETQ allows the detection of a threshold higher than the reset threshold. An alarm interrupt can be triggered with the output of this comparator. The intended use of this function is made, when a system uses a 5 V regulator with an unregulated input. In this case, the unregulated input, scaled down by a resistive divider, is fed to the RESETQ pin. With falling regulator input voltage this alarm interrupt is triggered first. Then the reset threshold is reached and the IC is reset before the regulator drops out. The time interval between the occurrence of the alarm interrupt and the reset may be used to save process data to nonvolatile memory. In addition, power-saving steps like turning off stepper motor drivers may be taken to increase the time interval until reset. 6.5.2. Internal Reset Sources During CPU-active modes, this IC contains four internal circuits that are able to generate a system reset: watchdog, supply supervision, clock supervision and FHR flag. 64 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C During power-saving modes, internal resets are generated that are not routed to pin RESETQ. However, a wake-up from any power-saving mode is treated as a fifth internal reset source and does pull RESETQ low. See chapter "Power Saving Module" for details. All these five internal resets are directed to the open-drain output of pin RESETQ. Thus a "wired or" combination with external reset sources is possible. The RESETQ pin is current-limited and therefore large external capacitances may be connected. All internal reset sources initially set a reset request flag. This flag activates the pull-down transistor on the RESETQ pin. An internal reset extension timer starts, as soon as no internal reset source is active any more. It counts 2048 fXTAL periods (for alternative settings refer to HW options register CR) and then resets the reset request flag, thus releasing the RESETQ pin. As long as the reset comparator on the pin RESETQ detects the low level, the overall IC is reset, except the PSM/RTC. The state of bits 6:0 in register CSW1, read directly after a system reset, allows to distinguish the cause of this last system reset (Table 6-5). 6.5.2.1. Supply Supervision A UVDD level below the supply supervision threshold VREFPOR, or an overload condition in the internal VDD or FVDD Regulators will permanently pull the pin RESETQ low and thus hold the IC in reset (see Fig. 6-3 on page 66). This reset source can be enabled/disabled by flag CMA in register CSW0 (see Section 6.5.2.2. on page 65). 6.5.2.2. Clock Supervision The clock supervision monitors the frequency at the oscillator input XTAL1 and also the frequency fSUP that is present at the input of the central clock divider (see Fig. 4-2). Fig 6-2 shows how the clock supervision works: Upon power-up the crystal oscillator starts to build up oscillation on pins XTAL1 and XTAL2. Initially, the internally available fXTAL/fSUP clock may show fluctuations and drop-outs. The internal reset extension timer starts counting fXTAL clocks as soon as 20 uninterrupted clocks, having a certain minimum amplitude, are detected, but it is reset when a drop-out period of 5 s appears. When the XTAL oscillation and thus fXTAL and fSUP have been stable over 2048 clocks, the reset extension timer may finish its travel and finally release pin RESETQ. V UVDD XTAL1 0 fXTAL <20 2048 Reset Ext. Count ~20 ~20 0 RESETQ Fig. 6-2: Clock supervision: Principle of operation Frequencies below the clock supervision threshold of approx. 200 kHz will permanently pull the pin RESETQ low and thus hold the IC in reset (see Fig. 6-3 on page 66). This reset source can be enabled/disabled by flag CMA in register CSW0. Frequencies exceeding the specified IC frequency are not detected. Clock and supply supervision are active after reset, but can be enabled/disabled by the clock-monitor-active flag CMA of register CSW0. Setting CSW0.CMA to 0 is recommended for test and evaluation purposes only. The clock supervision is switched off during power-saving mode. Every time the clock supervision is switched off (VDD Regulator is off) and is switched on again, it outputs a reset signal and sets flag CSW1.CLM. Micronas Feb. 10, 2005; 6251-579-1DS 65 CDC 32xxG-C DATA SHEET IDLE_5 WKST_5 + RES_5 1 ON_5 1 1 & core reset port reset VREFR RESETQ wake reset (internal signal) & Reset extension 8 or 2048 fXTAL clocks RESINT_5 WAKE_RES_5 reset in WDRES Watchdog >1 SQ R CSW0.CMA fXTAL fSUP POR wr CSW1 wr1 CSW0.FHR clock supervision & power on 1 CLS & 1 S R S R S R S R Q Q Q Q res CSW1 CSW1.FHR CSW1.CLM CSW1.POR CSW1.PIN CPUM=WKST CPUM=IDLE DQ R DQ R CSW1.WKST CSW1.IDLE Fig. 6-3: Reset logic block diagram 6.5.2.3. Watchdog The watchdog module serves to monitor undisturbed program execution. A failure of the program to retrigger the watchdog within a pre-selectable time will pull the pin RESETQ low and thus reset the IC (Fig. 6-3 and 6-4). This reset source is disabled by any POR and any WAKE-Reset. It is only enabled after a write access to location CSW1. The watchdog (Fig. 6-4) contains a down-counter that generates a reset when it wraps from zero to 0xFF. It is reloaded with the content of the watchdog timer register, when, upon a write access to location CSW1, watchdog trigger registers 1 and 2 contain bit-complemented values. An IC reset resets the watchdog timer register to 0xFF, thus setting the watchdog to the maximum reset interval. The three watchdog registers are programmed by writes to the same location CSW1. First write the desired watchdog timer value (only values between 1 and 255 are allowed): Interval x f 15 FAST and PLL modes: Value = ------------------------------- - 1 1 Interval x f 15 SLOW modes: Value = ------------------------------- - 1 128 On further writes, to trigger a reload of the counter, alternatingly write a retrigger value (routed to trigger register 1) (not necessarily the former timer value) and its bit-complement (routed to trigger register 2) to CSW1. Failure to reload will result in a counter underflow and a watchdog reset. Never change the retrigger value. Writing a wrong value to CSW1 immediately prohibits further reloading of the watchdog counter. The flag CSW1.WDRES is set as soon as the watchdog counter wraps to 0xFF. Thus, it is true after a watchdog reset. Only a supply supervision reset or a write access to CSW1 clears it. 66 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 2nd write & even CSW1 Trigger Reg1 8 3rd write & odd CSW1 Trigger Reg2 8 CSW1 1st write Timer Register 8 1st write clk PLL,FAST: f15 SLOW: f15 /128 = & & 1 load 8-Bit-Counter zero 2nd write & even 3rd write & odd reset in 1st write power on res CSW1 SQ R 1 DQ C S & SQ R WDRES CSW1.WDRES Fig. 6-4: Watchdog block diagram 6.5.2.4. Forced Hardware Reset Setting flag CSW0.FHR immediately forces the RESETQ pin low. This allows the SW to restart the whole system by HW reset. 6.5.2.5. Wake-Up Reset Module Entering one of the power-saving modes sets the corresponding flag in register CSW1, but does not pull RESETQ low. However, wake-up from one of the power-saving modes (signal WAKE_RES_5 in Fig. 6-3) does pull RESETQ low. CPU Interrupt Controller U-Ports High current ports LCD module Watchdog Status CPU Fast mode (fOSC). Interrupts are disabled. Priority registers, request flip-flops and stack are cleared. Normal mode. Output is tristate. Normal mode. Output is low. Registers are reset. No display. Inactive after POR and Wake-up. SW may activate. Unaffected in the other cases. Active. SW may deactivate. If during reset, the power was off, content is undefined. If power was not removed, last state is contained. If during reset, the power was off, content is undefined, except registers WSC, OSC, POL and SMX. If power was not removed, only registers OSC (flags RC, XK,XM), POL and SMX are reset. 6.5.4. Summary of Module Reset States After reset the IC modules are set to the reset state (Table 6-4) Table 6-4: Status after reset 6.5.3. External Reset Sources As long as the reset comparator on the pin RESETQ detects the low level, the overall IC is reset except the PSM/RTC. On this pin, external reset sources may be wire-ored with the IC internal reset sources, leading to a system-wide reset signal combining all system reset sources. Clock monitor SRAM, CANRAM PSM Micronas Feb. 10, 2005; 6251-579-1DS 67 CDC 32xxG-C 6.5.5. Reset Registers CSW0 7 w FHR 0 DATA SHEET POR WDRES Supply Supervision Reset (Tables 6-5, 6-6) Watchdog Reset (Tables 6-5, 6-6) Clock, Supply & Watchdog Register 0 6 x x 5 x x 4 x x 3 x x 2 x x 1 x x 0 CMA Table 6-5: Source of last hardware reset (CPU active modes) WDRES 0 1 0 0 0 WDRES 0 x x 4 WKST Reset Source IDLE CLM 1 Res This register controls the supply and cock supervision modules and allows to force a system reset. FHR Forced Hardware Reset w1: Reset forced w0: no action Enter an idle loop after setting this flag because, depending on the RESETQ external circuit, a number of opcodes will be executed before the reset becomes active. CMA Clock and Supply Monitor Active w1: Both Enabled. w0: Both Disabled. Can be written to zero only after supply or clock supervision reset and before first write access to register CSW1. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1 1 1 1 1 POR 0 0 0 1 0 FHR PIN external from RESETQ pin internal watchdog internal clock supervision internal supply supervision internal forced hardware The flags FHR to WDRES sum up the source of all HW resets that occurred since the last write to register CSW1. Any write access to CSW1 resets all flags to 0. Table 6-6: Source of last hardware reset (power-saving modes) WKST Reset Source IDLE CSW1 7 r TST - Clock, Supply & Watchdog Register 1 6 IDLE 0 5 WKST 0 4 FHR 0 3 CLM 0 2 PIN 0 1 POR 0 0 WDRES 0 Res CLM 0 The Reset state in the register frame above describes the state after a write to register CSW1. TST r1: r0: IDLE 6-6) WKST FHR CLM PIN TEST Pin State TEST is 1. TEST is 0. Wake Reset from IDLE Mode (Tables 6-5, Wake Reset from WAKE or STANDBY Mode (Tables 6-5, 6-6) Forced Hardware Reset (Tables 6-5, 6-6) Clock Supervision Reset (Tables 6-5, 6-6) RESETQ Pin Reset (Tables 6-5, 6-6) 0 1 0 1 0 0 x x 1 1 1 1 1 1 POR 0 x x FHR PIN external from RESETQ pin wake-up from WAKE/STBY wake-up from IDLE CSW1 7 w 1 1 Clock, Supply & Watchdog Register 1 6 5 3 2 1 0 Watchdog Time and Trigger Value 1 1 1 1 1 1 Res This register controls the watchdog module. See section 6.5.2.3. for details. 6.6. Test Registers Test registers are for manufacturing test only. They must not be written by the user with values other than their reset values (00h). They are valid independent of the TEST input state. In all applications where a hardware reset may not occur over long times, it is good practice to force a software reset on these registers within appropriate intervals. TST1 7 w 0 0 Test Register 1 6 5 4 3 2 1 0 For testing purposes only 0 0 0 0 0 0 Res 68 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C TST2 7 w 0 0 Test Register 2 6 5 4 3 2 1 0 For testing purposes only 0 0 0 0 0 0 Res TST3 7 w 0 0 Test Register 3 6 5 4 3 2 1 0 For testing purposes only 0 0 0 0 0 0 Res TST4 7 w 0 0 Test Register 4 6 5 4 3 2 1 0 For testing purposes only 0 0 0 0 0 0 Res TST5 7 w 0 0 Test Register 5 6 5 4 3 2 1 0 For testing purposes only 0 0 0 0 0 0 Res TSTAD2 7 w 0 0 Test Register AD2 6 5 4 3 2 1 0 For testing purposes only 0 0 0 0 0 0 Res TSTAD3 7 w 0 0 Test Register AD3 6 5 4 3 2 1 0 For testing purposes only 0 0 0 0 0 0 Res Micronas Feb. 10, 2005; 6251-579-1DS 69 CDC 32xxG-C DATA SHEET 70 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 7. Power Saving Module (PSM) To further reduce the power consumption one of three power-saving modes (WAKE, STANDBY and IDLE) can be selected. Non-power-saving modes are the CPU-active modes (DEEP SLOW, SLOW, FAST and PLL). Most of the core logic is switched off in a power-saving mode. Only HW necessary for wake-up (and RAM and port logic in IDLE mode) is supplied. Features - Power reduction down to 50 A possible - Real-time clock module (RTC) - Clock source: Built-in RC oscillator or XTAL - Up to 10 edge and level triggered wake ports - Wake sources: RTC module and/or wake ports - Polling Module for cyclic scan of the wake ports - Interrupt outputs of RTC module and port wake module Polling Module enable RC Oscillator 20..50kHz 4/5MHz 1 Up to ten Wake Ports Port Wake Module & H0.2 Core Logic AVDD, UVDD Analog Sections RTC Module WAKE_RES ICU ISN RTC Reset Logic ICU ISN WAPI Fig. 7-1: Context diagram The major task of the power saving module, as shown in figure 7-1, is to supply a wake-up signal (WAKE_RES) for the main system. This signal is necessary to get the IC out of a power-saving mode which otherwise cannot be left by any reset signal with exception of pin RESETQ. For that purpose it combines an RTC module for cyclic wake-up and a port wake module for event-driven wake-up. The power saving module is active all the time, during power-saving modes as well as during non-power-saving modes (CPU active modes). The WAKE_RES output signal can be generated during power-saving modes only. The RTC module has to provide the time of day accurately to the second and to generate an output signal which can be used to trigger an interrupt or a wake-up signal. The RTC module can be clocked by an external quartz oscillator or by a built-in RC oscillator. The polling module cyclically outputs a high pulse of programmable duration at port H0.2. Some of the RTC module taps are connected to the polling module for deriving the pulse period and duration. The port wake module merges several wake ports and outputs a signal that can be used to trigger an interrupt or a wake-up signal. Micronas Feb. 10, 2005; 6251-579-1DS 71 CDC 32xxG-C DATA SHEET 4/5MHz OSC.XM 4MXTL Oscillator en 1/8 SMX.MUX UVDD wake-up fPP fSS Poll Clk 5V/2.5V Mux LS SMX Out 20..50kHz OSC.RC OSC.SRC RC Oscillator en RTC Module 20-Bit Rel Reg SSR Sub Sec Cnt SSC 3 7 10 14 10..19 SMX.BYP fS load 1Hz fm fh fd SEC MIN HR 1 2 4 8 16 32 1 2 4 8 16 32 1 2 4 8 16 24 RTCC.SEL Mux RTC Out CLK Mux fPC POL.OE POL.ENA Polling Module WSC.RTC CPUM=WKST CPUM=IDLE RES_5 WSC.P WSC.AST WPMx.MOD UPort PPort CANx-RX CMOS Threshold Wake In Edge/Level Trigger Mode & Enable trigger & SQ R WUS.WPx 1 1 5V/2.5V LS ISN WAPI WKST_5 SQ R IDLE_5 SQ R enable & Poll Clk Delay Counter POL.DEL POL.PER Mux Poll Period fPP & Wake Out WUS.RTC SQ R Poll Out H0.2 5V/2.5V LS ISN RTC & 1 1 1 & wake-up ON_5 WAKE_RES 10x Port Wake Module Fig. 7-2: Power-saving module functional block diagram 7.1. Functional Description The power-saving logic combines all wake-up sources. It is completely supplied by UVDD. It contains an RC oscillator, a 20-bit sub-second counter, an RTC, multiplexers to select different taps of the sub second counter or of the RTC, a polling module and the logic for up to ten wake ports. The RTC module output can generate an interrupt or a wakeup signal. All wake ports can generate a collective interrupt or a wake-up signal. The polling module can drive an H-Port and generate a strobe signal, which allows a wake port to trigger on a dedicated input level. Several internal clock signals can be output via CO0. 7.1.1. RTC Module The RTC module is mainly composed of a sub-second counter (SSC) and its reload register (SSR), and the realtime counter's second, minute and hour counters. The input clock for the sub-second counter (fSS) can be selected between the external quartz oscillator clock divided by 8 or an internal RC oscillator clock. The reload value SSR shall be selected so that the output signal of the SSC (fS) corresponds with a one Hertz clock. The signal fS is the reload signal for SSC, which is a down counter, as well as the input clock to the second counter (RTC.SEC). The second counter clocks the minute counter (RTC.MIN) which on his part clocks the hour counter (RTC.HR). All of them are up counters. 72 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C The polling period has to be set equal or greater than four times the polling delay. All stages of the three counters can be selected to generate an interrupt or a wake-up signal. The RTC cannot be stopped during debug mode by flag CR.STPCLK=1. 7.1.3. Port Wake Module There is a trigger mode logic (level or edge sensitive) and a wake source flag for each wake port. The wake out input is a signal from the polling module. The falling edge generates a strobe pulse which is used to sample the level of the wake In input and set the corresponding wake source flag if necessary. An alternative strobe signal can be used (WSC.AST=1), if there is no RTC subsystem (with polling logic) implemented. The corresponding WPx flag in register WUS will be forced to high as long as the programmed condition (high or low level) is met at the wake port. Please see figure 7-6 for details. The selected strobe signal source is valid for all wake ports. Mixing of the strobe signal sources (polling and alternative) is not possible. The wake flags of all wake ports are located in the wake-up source register WUS. The trigger events which can set the wake flags can be configured in the wake-up pin mode registers WPM0 to 8 either in field MOD0 or MOD1. Please refer to table 7-7 for details about allocation of mode registers and wake ports. The output of each wake port is connected to an or gate, whose output can generate a wake port interrupt as well as a wake-up signal. 7.1.2. Polling Module The polling module periodically activates the output signal "wake out" which can be enabled by SW to drive port H0.2 (Poll Out). The rising edge of the polling period input (fPP) defines the begin and the polling clock (fPC) input together with the delay counter defines the duration of the high time. This can be used to cyclically flash a LED or to feed a current into an external circuit. The falling edge of the wake out signal is used to sample the input level of all wake ports (WPx) which are configured for high or low level trigger mode. Those configured ports will set the corresponding WPx flag in register WUS with the falling edge of the strobe signal. Please refer to figure 7-5 for timing details on the wake out and the strobe signals. Due to the adjustment mechanism by the 20-bit reload register, the polling period is not always constant. Depending on the reload value, the polling period may vary between 0.5 and 1.5 nominal polling periods at the point of reloading. 7.2. Registers the next reload of the SSC. It can be forced immediately by writing a one to the flag LD with the same write access. A read access returns the current source select, not the requested. Thus read-modify-write instructions have to be used carefully. OSC 7 r/w RC 1 Oscillator Source Register 6 XK x 5 XM 1 4 x 3 LD 2 x No HW reset 1 SRC 0 0 Offs Res SSR 7 r/w r/w r/w r/w x x Sub Second Reload Register 6 x x RC r/w1: r/w0: RC oscillator enable disable 5 x x 4 x x 3 x 2 x 1 x 0 x 3 2 1 0 Offs XK External 32kHz XTAL (not available) r/w1: enable r/w0: disable Write to zero for future compatibility. XM r/w1: r/w0: LD r: w1: w0: 4MHz XTAL always enabled disabled during power-saving modes Load SRC and SSC Always read as zero Immediately selects the oscillator source according to SRC and loads the register SSR to the SSC. No action Bit 19 to 16 Bit 15 to 8 Bit 7 to 0 No HW reset Res SRC Oscillator Source Select r/w0: 4/5MHZ XTAL divided by 8 selected r/w1: Don't use, factory test only r/w2: RC oscillator selected r/w3: Ground (don't use for compatibility reasons) Writing to SRC does not select a new oscillator source immediately. This will be done automatically together with For typical settings refer to table 7-1, the values 0 and 1 are not allowed. To avoid programming unexpected values, never write single bytes of the SSR on their own, but always all 3 bytes without being interrupted by SSC read. This is necessary, as for reading SSC the register hardware uses the same buffer registers as for writing SSR. Writing SSR does not load the SSC immediately. This will be done automatically together with the next reload of the SSC. Immediate loading of the SSC can also be forced by setting OSC.LD. Wait one fIO cycle between write and read access to SSR because it lasts one bus cycle until a written value becomes valid. Micronas Feb. 10, 2005; 6251-579-1DS 73 CDC 32xxG-C w1: w0: 1 x DATA SHEET SSC 7 r r r r x x Sub Second Counter 6 x x Clear No modification Wake Port x Wake Port was trigger source No trigger Clear No modification 5 x x 4 x x 3 x 2 x 0 x 3 2 1 0 Offs Bit 19 to 16 WPx r1: r0: w1: w0: Bit 15 to 8 Bit 7 to 0 No HW reset Res A read access to byte 0 of the SSC latches the bytes 1 and 2. This mechanism grants consistent read access to the SSC. For proper interrupt generation some peculiarities in operating this register have to be considered. All set bits must be cleared by writing back the whole pattern that was read before. Always read and clear (write back) the whole register (byte 0 first), even if only flags in byte 0 are in use. Every write access to byte 1 will produce an interrupt as long as WUS contains a one. WPMx RTC 7 r/w r/w r/w r/w x x x x Wake Port x Mode Register 6 5 MOD1 Real Time Counter 6 x x x x No HW reset 7 2 1 x 4 3 x 2 1 MOD0 0 0 Offs 5 x x 4 x 3 x 0 x 3 Offs r/w x x HR MIN SEC No HW reset 2 1 0 Res Res MODy Trigger Mode (Table 7-3) Trigger mode for wake port WPx+y. For assignment of wake port and mode field please refer to table 7-7. Reading SEC latches MIN and HR. Writing HR simultaneously loads MIN and SEC to the corresponding counters. This mechanism allows consistent read and write access. Since reading and writing use the same latches, do not mix these access types. Wait one fIO cycle between write and read accesses to RTC because it lasts one bus cycle until a written value gets valid. HR r/w0 to 23: MIN r/w0 to 59: SEC r/w0 to 59: Hour Counter Minute Counter Second Counter POL 7 r/w r/w x ENA OE Polling Register 6 CLK x 0x00 5 4 x 3 2 PER DEL 1 0 1 0 Offs Res CLK PER ENA r/w1: r/w0: OE r/w1: r/w0: 1 0 0 Res Offs Select Polling Clock (Table 7-5) Select Polling Period (Table 7-4) Enable Polling Module enable disable Enable Polling Output enable disable RTCC 7 r/w x RTC Control Register 6 x 5 x 4 3 2 SEL No HW reset SEL Select RTC Output (Table 7-2) DEL Select Polling Delay Time r/w1 to 31: Delay time = DEL/fPC r/w0: Delay time = 32/fPC A write access to DEL immediately loads the 5-bit down counter. The delay time defines the duration of the Wake Out signal (Fig. 7-5). WUS 7 r/w r/w RTC WP7 Wake-Up Source Register 6 x WP6 WSC 0 WP8 WP0 1 0 Res Offs r/w Wake Source Control 6 x 5 x WP5 4 x WP4 3 x WP3 2 x WP2 1 WP9 WP1 7 x 5 x 4 x 3 x 2 AST 1 RTC 0 P 0 Offs 0x00 after UVDD power-up Res No HW reset RTC r1: r0: Real Time Clock RTC was trigger source No trigger AST r/w1: r/w0: RTC r/w1: Alternative Strobe Alternative strobe input Wake out signal from Polling Logic RTC Wake-up Enable enable 74 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C r/w0: disable Neither WUS.RTC nor the RTC interrupt source output are affected. P Port Wake-up Enable r/w1: enable r/w0: disable Neither WUS.WPx nor the WAPI interrupt source output are affected. Table 7-2: SEL usage SEL 0 1 second counter taps Tap# Gnd 1 2 4 8 16 32 1 minute counter taps 2 4 8 16 32 1 2 hour counter taps 4 8 16 24 Activation Never Every second Every 2 seconds Every 4 seconds At second 8, 16, 24, 32, 40, 48, 56 At second 0, 16, 32, 48 At second 0, 32 Every minute Every 2 minutes Every 4 minutes At minute 8, 16, 24, 32, 40, 48, 56 At minute 0, 16, 32, 48 At minute 0, 32 Every hour Every 2 hours Every 4 hours Every 8 hours At hour 0, 16 Every day SMX 7 r/w BYP Signal Multiplexer Register 6 x 2 0 0 Res Offs 5 x 4 x 0x00 3 x 2 1 MUX 3 4 5 BYP r/w1: r/w0: Bypass SSC RTC is clocked by fSS (test) RTC is clocked by fS (1Hz) 6 7 8 9 MUX Signal Multiplexer (Table 7-6) Defines a signal which is output as SMX Out. Table 7-1: SSR: Typical settings for fS = 1Hz XTAL 1/8 Period Reload Value 500.000 625.000 32.768 Step Resolution 1 ppm 0.8 ppm 16 ppm 10 11 12 13 14 15 16 17 18 19..31 4 MHz 5 MHz 500 kHz 625 kHz 2 s 1.6 s 30.5 s 20...50 kHz RC Don't use SEL = 4, 5, 6, 10, 11, 12 and 17 do not produce isochronous intervals. Micronas Feb. 10, 2005; 6251-579-1DS 75 CDC 32xxG-C DATA SHEET Table 7-3: MOD usage MOD 2 x 0 0 0 1 1 1 1 0 0 1 1 0 1 1 0 0 1 0 1 1 0 1 Disabled Rising edge Falling edge Rising and falling edge High level 1) Low level 1) Both levels (every strobe signal) 1) Trigger Modes Table 7-5: CLK usage CLK 0 1 2 3 Sub Sec Tap# 3 7 10 14 fPC fSS/2TAP# Table 7-6: MUX usage MUX 0 1 2 Name UVDD fSS fS (1Hz) (wake-up) (wake-up) wake-up fPP 1) Poll Clk logic high level SSC input (calibration) SSC output (adjustment) Test (factory use only) 1) In WAKE mode with alternative strobe only. Table 7-4: PER usage PER 0 1 2 : 9 10 11 12 Second Counter 13 14 15 TAP# Sub Second Counter 10 11 12 : 19 1 2 4 8 16 32 1 Hz 0.5 Hz 0.25 Hz fPP (rising edge) fSS/2TAP# 3 4 5 6 7 1) If POL.PER =10 (1Hz selected), POL.ENA has to be enabled. No 1 Hz pulses can be observed at SMX out otherwise. Table 7-7: Wake ports WPMx 0 2 4 6 8 Name Basic Funct. U1.7 P1.0 P1.1 U1.3 U0.7 U4.3 U2.1 U6.1 U8.5 U8.3 MODy 0 1 0 1 0 1 0 1 0 1 at second 4, 12, 20, 28, 36, 44, 52 at second 8, 24, 40, 56 at second 16, 48 WP0 WP1 WP2 WP3 WP4 WP5 WP6 WP7 WP8 WP9 Isochronous intervals can only be achieved by PER = 10, 11 or 12. 76 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 7.3. Operation of Power Saving Module Before entering a power-saving mode, the necessary wakeup sources have to be configured carefully. The reset/wakeup reason in register CSW1 and the wake-up source register WUS have to be cleared. Please see section "CPU and Clock System" for information on entering a power-saving mode. auxiliary VDD generator. When VDD is active again, the signal CLS is cleared and the reset extension is started. After the reset extension has finished, the pin RESETQ is released and the core reset signal is pulled to low. The flag CSW1.IDLE is set. The CPU starts execution at the reset vector and can read the reset/wake-up reason in register CSW1. The wake-up source can be read in register WUS and should be cleared thereafter, otherwise wake port interrupts are not possible. 7.3.1. Configuration of Wake Sources 7.3.1.1. Port Wake Module If an external event driven wake-up is necessary, the port wake module has to be configured according to section 7.6. The register WUS has to be cleared. Flag WSC.P has to be set, enabling the port wake module output signal to generate a wake-up signal by setting signal WAKE_RES. If a wake port is to be operated in polling mode (level triggered), configuration of RTC module and polling module is necessary as described in sections 7.4. and 7.5. 7.3.1.2. RTC Module If a cyclic wake-up is necessary, the RTC module has to be configured according to section 7.4. Flag WUS.RTC has to be cleared. Flag WSC.RTC has to be set, enabling the WUS.RTC output signal to generate a wake-up signal by setting signal WAKE_RES. 7.3.5. Precautions The SW has to guarantee the ability of wake-up by careful configuration of the wake logic. Especially the necessary wake ports have to be configured as input. Verifying the necessary configuration before switching to a power-saving mode will enhance the safety. Enabling wake-up by pin only is dangerous. Accidentally entering a power-saving mode or if a flag is modified by electrical over stress (EOS) in a power-saving mode, may lead to an IC which can't be wakened. From an inadvertently entered power-saving mode, with no wake source being enabled, neither the watchdog nor the clock supervision nor any other internal reset source, but only an external reset on pin RESETQ may recover the device. As neither the VBG generator nor the RESET comparator are enabled during power-saving modes, proper CMOS input levels (Vil = UVSS 0.3 V and Vih = UVDD 0.3 V) are required on pin RESETQ during a wake-up reset. The external circuitry must allow the device to establish WRVil on that pin. The specified power-saving mode current consumption values are only obtainable when CMOS input levels (Vil = xVSS 0.3 V and Vih = xVDD 0.3 V) are applied to: - in IDLE mode all H-, P- and U-Ports - in WAKE/STANDBY modes all, not only the configured, wake ports. If an RTC-/Polling module is not used, it is advisable to switch it off to reduce current consumption. Its outputs should be disabled. 7.3.2. Configuration of Interrupts During CPU active modes, the RTC module and the port wake module can be operated as interrupt sources. The ICU and the corresponding ISNs have to be configured according to section "IRQ Interrupt Controller Unit". 7.3.3. WAKE/STANDBY With writing WAKE/STBY to SR1.CPUM, the VDD regulator is immediately switched off and a core and a port reset signal is generated. A wake-up signal sets WAKE_RES to one, immediately pulling pin RESETQ to low. This sets register SR1.CPUM to FAST, disabling the WAKE_RES output of the power saving module and enables the VDD generator. When VDD is active again, the signal CLS is cleared and the reset extension is started. After the reset extension has finished, the pin RESETQ is released and the core and port reset signals (RES_5, RESPORT, RESCORE) are pulled low. The flag CSW1.WKST is set. The CPU starts execution at the reset vector and can read the reset/wake-up reason in register CSW1. The wake-up source can be read in register WUS and should be cleared thereafter, otherwise wake port interrupts are not possible. 7.3.4. IDLE With writing IDLE to SR1.CPUM, the VDD regulator is immediately switched off, the auxiliary VDD generator is switched on and a core reset signal is generated. A wake-up signal sets WAKE_RES to one, immediately pulling pin RESETQ to low. This sets register SR1.CPUM to FAST, disabling the WAKE_RES output of the power saving module and enables the VDD generator and disables the Micronas Feb. 10, 2005; 6251-579-1DS 77 CDC 32xxG-C 7.3.6. Timing DATA SHEET UVDD RESETQ RES_5 WAKE_RES IDLE_5 WKST_5 VDD RESPORT RESCORE CLS 2048 Clk RESINT_5 Fig. 7-3: Power-on reset 78 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C UVDD RESETQ RES_5 WAKE_RES CPU IDLE_5 CPU WKST_5 VDD RESPORT RESCORE CLS 2048 Clk RESINT_5 Fig. 7-4: Switching to WAKE/STANDBY and IDLE and wake-up 7.4. Operation of RTC Module 7.4.1. Reset With the exception of the oscillators, which are enabled by every reset (OSC.RC = OSC.XM = 1), most parts of the logic will never be reset. This means that after every reset the unneeded oscillator has to be switched off. Further, the whole logic has to be initialized after a power-on reset. An application that does not require RTC and polling module can inhibit the outputs of the modules by writing a 2 to OSC.SRC, a 0 to OSC.RC, a 1 to OSC.LD and a 0 to RTCC.SEL after every reset. This setting also minimizes the power consumption. frequency. Writing the desired oscillator source in field SRC, enabling it if necessary and setting flag LD in register OSC immediately selects the new oscillator source and loads SSR to SSC. - Changing the SSR Due to temperature or other dependencies of the oscillator it may be necessary to adjust the reload value in the SSR register from time to time. This can be done within the RTC interrupt service routine. Write the new reload value to the SSR register. Make sure that this will be completed before the next underflow of the SSC, which simultaneously loads the SSC with the new SSR value and also switches the oscillator source with the beginning of the next second. - Changing the oscillator source Due to switching to a power-saving mode it may be necessary to change the oscillator source. This can be done within the RTC interrupt service routine. Select the desired oscillator source in OSC.SRC and write the corresponding reload value to the SSR register. Make sure that both will be completed before the next underflow of the SSC, which simultaneously loads the new SSR value to the SSC and switches to the new oscillator source with the beginning of the next second. Precaution: Changing the oscillator source may cause a fragmentary clock pulse. This may result in wrong SSC and/ 7.4.2. Oscillator Source and Sub-Second Counter The sub-second counter (SSC) generates a 1 Hz output signal at underflow (0x00000 to 0xFFFFF). This signal loads the SSC with the content of the SSR register and switches the oscillator source select multiplexer to the desired oscillator according to the SRC field in the OSC register. This load signal can be forced by writing a one to flag LD in register OSC. There are three necessities for when to change SSR and OSC.SRC: - Starting the SSC for the first time (after power on) Because OSC.SRC is not reset by HW, an oscillator source must be selected and enabled. The SSR has to be loaded with the reload value necessary for a 1 Hz output Micronas Feb. 10, 2005; 6251-579-1DS 79 CDC 32xxG-C or RTC values and unwanted interrupt or wake pulses. Changing the oscillator source makes it necessary to: 1. Disable all output signals of the power saving module (ISN RTC, ISN WAPI, POL.OE=WSC.RTC=WSC.P=0). 2. Switch to the new oscillator source. 3. Initialize SSR, RTC and POL. 4. Clear WUS (WUS = 0xFFFF). 5. Clear the pending flags of the corresponding ISNs. 6. Enable the output signals and interrupts again. DATA SHEET Precaution: Please be aware that modifying RTC or RTCC may result in additional negative edges on RTC Out. If no measures are taken, these edges will generate unwanted interrupts. It is recommended in this situation to temporarily disable the RTC interrupt. But, in order not to affect the intended interrupts, a 1 Hz clock pulse must be avoided during modification of RTC or RTCC. A solution that takes care of the above-described situation, is reading SSC and modifying RTC or RTCC only, if sufficient time is available to intercept the unwanted interrupt before the next 1 Hz clock pulse occurs. 7.4.3. Access to SSC and RTC SSC and RTC are periodically altered by clock pulses. Even if the 32 kHz subsystem is clocked by the 4/5 MHz oscillator, a CPU access to SSC and RTC may be corrupted by a clock pulse. As this situation cannot be avoided, the SSC or the RTC register have to be read twice. If the difference between the two accesses is illogical, the read has to be repeated. After a write to register RTC it has to be read and compared to the desired value. If there is a difference, write, read and compare have to be repeated. Since the RTC is clocked not faster than in second distance, a read or write access to register RTC can be done in the RTC-ISR. Such an access is safe and guarantees a correct result as long as the RTC-ISR is finished before the next clock alters the RTC. 7.4.6. Inactivation Disabling of the RTC module can be done by selecting the RC oscillator (OSC.SRC=2) and disabling this source (OSC.RC=0) by simultaneously writing a one to OSC.LD. Though selecting ground (OSC.SRC=3) would also disable the 32 kHz subsystem, this should be avoided to be compatible with future extensions. Setting RTCC.SEL to zero avoids unwanted interrupts after a non-power-on reset. 7.4.7. Signal Multiplexer Different internal signals can be switched to SMX Out. The internal signal can be selected via register SMX.MUX. The possible signals are shown in table 7-6. Only the signals fSS and fS are of general interest, the remaining signals may be used, but are intended for testing purposes. The signal fSS is useful for measuring the quartz frequency and calculating the corresponding reload value for the subsecond counter with external equipment. The signal fS is useful for re-adjustment of the sub-second counter, with the help of, e.g., an XTAL-driven CAPCOM counter, when driven by the internal RC oscillator. The bypass switch (SMX.BYP) allows to bypass the SSC and directly feed fSS into the second counter. This feature is intended for testing purposes only and is to be written to zero. 7.4.4. RTC Output Multiplexer All the taps of the second, minute and hour counters are connected to a multiplexer (Table 7-2) and can be selected as output by register RTCC.SEL. The output of this multiplexer can generate an RTC interrupt as well as a wake-up signal. 7.4.5. RTC Interrupt Beneath above described initialization, the ICU and the corresponding ISN has to be initialized. The RTC has its own ISN and interrupt vector. Thus, further investigation about the interrupt source is not necessary. After an interrupt the flag WUS.RTC is set. The register WUS.RTC is not necessary for, and has not to be handled by the RTC-ISR. 7.5. Operation of Polling Module 7.5.1. Reset The whole logic is reset by every reset, even wake-up from power-saving mode resets the polling module. This means that the logic has to be initialized after every reset. The port H0.2 has to be configured as normal, out, low for operation as polling output. Select fPC (POL.CLK) and fPP (POL.PER). Enable input and output (POL.ENA, POL.OE) and load the delay counter reload register (POL.DEL) with a non-zero value. 7.5.2. Initialization and Start The polling module needs the RTC module to be running, because the polling clock fPC is derived from sub-second counter taps, and the polling period fPP is derived from subsecond counter taps or second counter taps. See section 7.4. for RTC module initialization. The enable input (POL.ENA) and the output (POL.OE) has to be disabled. 80 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C poll period poll clk poll period start poll delay wake out 0 strobe 3 2 1 0 0 3 Fig. 7-5: Polling timing 7.5.3. Stop Disable all inputs and outputs (POL.ENA=0, POL.OE=0). 7.5.4. Restart Set POL.ENA and POL.OE to one. Load the delay counter reload register (POL.DEL). 7.6. Operation of Port Wake Module WPMx.MOD 210 rising delay & Wake In from port & falling delay & Delay & strobe & high 1 trigger Wake Out from Polling Logic WSC.AST strobe 1 alt. strobe & low strobe Fig. 7-6: Edge/level trigger logic 7.6.1. Reset Neither the wake-up source register (WUS) nor the wake-up pin mode registers (WPMx) are reset to a defined value by any reset source. abled. The source of the strobe signal has to be selected by flag WSC.AST if a level triggered mode is to be used. The whole register WUS has to be cleared. 7.6.3. Operation The port wake module can be operated by polling, it can generate an interrupt (ISN WAPI) or it can be used to generate a wake-up signal to leave a power-saving mode. To use a level triggered mode of a wake port the RTC module and the polling module have to be configured to provide 7.6.2. Initialization The corresponding ports must be configured normal in. For every wake port which is to generate a wake-up signal, the trigger mode in the WPMx register has to be programmed. For every wake port not generating a wake-up signal, the trigger mode in the WPMx register has to be dis- Micronas Feb. 10, 2005; 6251-579-1DS 81 CDC 32xxG-C the necessary "wake out" signal. The signal "wake out" is necessary for a strobe pulse at the falling edge of "wake out". If no RTC/Polling module is available or should not be used, an alternative strobe signal can be used by setting flag WSC.AST to one. As long as WSC.AST is set and the programmed trigger level is applied to the corresponding pin, the flag WUS.WPx is set and cannot be reset by the SW. If more than one wake port is operated with the alternative strobe signal, WPMx.MOD has to be disabled before WUS.WPx can be cleared. Clearing WSC.AST only during the WUS clearing procedure does not help in this case. Interrupts of other wake ports can be lost if the high or low time is too short. Set WSC.AST to 1 if a wake port is used as CAN bus wakeup, otherwise it is possible that a CAN telegram is always strobed at its high level. In this case the CAN telegram cannot arouse the system. The selected strobe signal source is valid for all wake ports. Mixing of the strobe signal sources (polling and alternative) is not possible. If only edge-triggered mode is used, the RTC module and the polling module are not necessary for correct operation of the port wake module. DATA SHEET 7.6.4. Wake-up from Power-Saving Mode In addition to the initialization described above, it is necessary to enable the port wake module as wake-up source by register WSC flag P. After wake-up the reason can be read in register WUS. It should be cleared after reading, otherwise neither wake-up nor wake port interrupt via ISN WAPI is possible. 7.6.5. Wake Port Interrupt Beneath above described initialization, the ICU and the corresponding ISN has to be initialized. All wake ports are directed to a single ISN and interrupt vector. After an interrupt the source can be read in register WUS. It should be cleared after reading, otherwise no further wake port interrupts via ISN WAPI are possible. Precautions Parallel usage of a P-port as analog and wake port input is possible, but not recommended. In this case, the Schmitt Trigger input circuit is enabled. This is the reason why input levels other than AVSS and AVDD may cause quiescent currents in the Schmitt trigger circuit and thus lead to higher power consumption. 82 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 8. JTAG Interface This module provides JTAG style access to five internal scan chains. These allow testing, debugging, EmbeddedICE and embedded trace module (ETM) programming. The scan chains are controlled by a JTAG style test access port (TAP) controller. For further details on operating the TAP controller, EmbeddedICE and ETM, please refer to the "ARM7TDMI Data Sheet" (Document Number: ARM DDI 0029), "Embedded Trace Macrocell Specification" (Document Number: ARM IHI 0014) and "ETM7 Technical Reference Manual" (Document Number: ARM DDI 0158). Features - 2 interfaces selectable - Access to CPU periphery - Access to EmbeddedICE - Access to ETM (embedded trace module) 8.1. Functional Description TMS JTAG TAP Controller TDI TDO nTRST DBG.DISA POR ON_5 1 & 1 & MUX 0 ETMS ETDI ETDO nTRST TCK/U3.2 TMS/U3.1 TDI/U3.0 TDO/U3.3 TEST2 2) & CR.JTAG 1) VDD @ PQFP128 2) Availability of Pull-down see section "Packages and Pins" 1) Fig. 8-1: JTAG interface block diagram The TAP controls the access to the scan chains. Scan chain 0 allows access to the entire periphery of the CPU. Scan chain 1 is a subset of the scan chain 0. Scan chain 2 allows programming of the EmbeddedICE debug module. Scan chain 3 is reserved for the boundary scan of the pads of the packaged device. Scan chain 6 allows programming of the ETM. Table 8-1: Scan chains Number 0 1 2 3 6 Size [Bit] 105 33 38 40 Function ARM7 Macrocell Part of scan chain 0 EmbeddedICE reserved for boundary scan ETM Two interfaces can be selected to access the TAP controller. The selection has to be done by the control register flag CR.JTAG and the pins TEST2 and nTRST. 8.1.1. Application JTAG Interface The application JTAG interface is connected to U-Ports U3.0 to U3.3 and to pin TEST2. The application JTAG interface is available if enabled and the external circuit layout allows it. It is enabled if the TEST2 pin is high, the nTRST pin is low and the flag CR.JTAG is set to one. In detail, during reset, CR.JTAG is forced to zero and U-Port U3.3 (JTAG TDO) is tristate. If TEST2 pin is high and CR.JTAG is set during operation, U-Port U3.3 is forced to Port, Special, Output mode until programmed by SW. Otherwise the application JTAG interface could not be operated without internal SW support. To avoid conflicts between JTAG mode and SW control on this port bit, never mix these two modes in one application. The application SW must not initialize the involved U-Ports if flag CR.JTAG is set to one. The flag CR.JTAG is modified by the Special Function ROM too, see section "Special Function ROM" for details. Micronas Application JTAG Ifc Emulation JTAG Ifc CPGA257 only TCK ETCK Feb. 10, 2005; 6251-579-1DS 83 CDC 32xxG-C 8.1.2. Emulation JTAG Interface The emulation JTAG interface is connected to dedicated pins of the emulation parts (CPGA257 package). Series parts (PQFP128 package) do not provide this interface. It is enabled as long as the application JTAG interface is disabled. DATA SHEET JTAG probe and TEST2 pin and disabling the driver during reset. The reset state can be detected by sensing the RESETQ pin. The threshold voltage of the external logic must be higher than the minimum recommended reset inactive input voltage RVim (1.5 V) of this IC. Use, for example, the 74HC14 Schmitt Trigger (not the HCT variant!). Figure 8-2 shows an example of the external circuit. 8.1.3. Boundary Scan The boundary scan is not implemented in this IC. UVDD 4k7 74HC14 RESETQ 8.1.4. Pin TEST2 Refer to section "Electrical Characteristics" for details. Besides JTAG, the pin TEST2 controls the behavior of the IC during reset. Refer to section "Core Logic" for further details. nTRST from host TEST2 NC7SZ125 4k7 Jumper defines reset level 8.1.5. External HW Requirements The external circuit has to make sure that the TEST2 pin is driven to the required level during reset and switched to the JTAG probe after reset so that the pin can be controlled by the probe. This can be done by connecting a driver between UVDD Fig. 8-2: TEST2 pin external circuit diagram for application JTAG interface 8.2. Registers DISA w1: 2 x DBG 7 w x Debug Register 6 x 5 x 4 x 3 x 1 x 0 DISA 0 Offs w0: Disable Voltage Generators, JTAG/ETM Standard: Debug data lost during powersaving modes because supply is disabled. Survive mode: Regulators don't shut off power during power-saving modes, and debug data survive wake reset. 0x01 (after UVDD power-up) Res 8.3. External Circuit Layout The emulation JTAG interface uses TTL level input comparators. The emulation JTAG inputs ETCK, ETMS, ETDI and nTRST need external pull-up resistors to EVDD. This has to be done in such a way that the TAP controller sees a logic one if the emulation JTAG interface is enabled but not driven. The application JTAG interface shares its input and output pins with the I/O of U-Ports. The external circuit layout has to be done carefully in order to guarantee functionality of the JTAG interface. As long as the application JTAG interface is enabled and not driven, the TAP controller inputs TMS and TDI must see logic one level. If it is enabled and driven, the external application circuit shall not influence proper operation of the JTAG interface. The external host must be able to drive the levels at the inputs TCK, TMS and TDI to CMOS logic one and logic zero levels and it must be the only source of these signals. The TAP controller must be able to drive the output TDO to both CMOS levels, logic one and zero, and must be the only source of this signal. Common JTAG tools expect to see pull-up resistors at nTRST (TEST2), TCK,TMS and TDI. 8.4. JTAG ID The JTAG ID is not implemented in this IC. The JTAG TAP controller contains a HW coded JTAG ID which can be read serially via the JTAG interface. The CPU can't access this ID. Bits 1 to 19 are manufacturer-defined. Bits 0 and 20 to 31 are ARM-defined. 84 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Version Part Number 20 19 31 28 27 26 25 24 23 12 11 Device Number 1 c2 c1 c0 Family Manufacturer ID 10 1 Fig. 8-3: JTAG ID format Bit 31 to 28 0: 1: 2: Bit 27 0: 1: Bit 26 0: 1: Bit 25 Bit 24 0: 1: Bit 23 to 20 7: 9: A: etc. Version ARM core revision 0. ARM core revision 1. etc. ARM core ID. Non ARM core ID. Capability bit 2 Standard part. `E' part. Capability bit 1 (Reserved) Capability bit 0 Hard macro. Synthesizable. Family ARM7. ARM9. ARM10. Bit 19 to 12 Device Number Manufacturer device number 0 to 255. Bit 11 to 1 Manufacturer ID Manufacturer ID is the compressed JEDEC code (0x06C). Bit 0 Marker Fixed value. The necessity of using bits 19 to 12 as manufacturer device number forces us to use the Non-ARM core ID format of the JTAG ID. This is the reason why some debug tools cannot use auto configuration, but must be configured by the user for the correct core and revision. The part number shall be selected in a way that no two component types in the same package with TAP pins in the same location have the same part number. Micronas Feb. 10, 2005; 6251-579-1DS 85 CDC 32xxG-C DATA SHEET 86 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 9. Embedded Trace Module (ETM) This module provides instruction and data trace capability. The ETM is controlled by a JTAG style test access port (TAP) controller. For further details on the installed Rev1A please refer to the "Embedded Trace Macrocell Specification" (Document Number: ARM IHI 0014) and the "ETM7 Technical Reference Manual" (Document Number: ARM DDI 0158). Features - Instruction trace - Data trace - Trace before, about, after trigger - Trigger and filter capabilities - Access to "Embedded Trace Module" - Normal trace data format - Full-rate and half-rate clocking - 4/8/16-bit maximum port width 9.1. Functional Description TRACECLK ETM7 Rev1A PIPESTAT0 to 2 TRACEPKT0 to 15 TRACESYNC EXTTRIG CLK PWRDOWN DBGRQ nRESET 0 TCK TMS JTAG TAP Controller TDI TDO nTRST DBG.DISA POR ON_5 1 & & CR.JTAG RESETQ CR.TETM DBGRQ DBGACK ARM and EmbeddedICE BREAKPT EXTERN0 EXTERN1 RANGEOUT0 RANGEOUT1 nEXEC nRESET nRESET & 1 MUX TCK/U3.2 TMS/U3.1 TDI/U3.0 TDO/U3.3 TEST2 Application JTAG Ifc 1 FSYS ETCK ETMS ETDI ETDO nTRST Emulation JTAG Ifc 1 & Fig. 9-1: ETM interface block diagram Micronas Feb. 10, 2005; 6251-579-1DS 87 CDC 32xxG-C The ETM is controlled via scan chain 6 of the JTAG interface. The process of remapping or loading code to RAM and executing there, is a problem for the ETM because one address can contain different code (overlay). The solution is based on the requirement that the memory map into which overlays are loaded, exists in multiple places in the address space. The memory controller of the IC decodes the 24 LSB address lines A0 to A23. This results in a memory map of 16 MByte. This memory map is repeated 256 times within the 32-bit ARM core address space of 4 GByte. Thus it is possible to have one static image of the code being executed for the trace tool, with different possible overlays statically linked into the appropriate area of the address space. Loading code into the RAM and executing it there means, copying the code into the RAM and then jumping to its overlay. The ETM sees the full 32-bit address and reports this jump to the trace tool which has the static image with a memory map for each configuration at different places of its address space. The memory controller sees the 24 lower address lines only, therefore the jump is directed to the correct location. The supported trace features are listed in Table 9-1. DATA SHEET Table 9-1: Trace features Features Demultiplexed trace data format Multiplexed trace data format Normal trace data format Full-rate clocking Half-rate clocking Maximum port width Supported 4/8/16-bit 88 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 10. Memory Patch Module V1.0 The memory patch module allows the user to modify data words within the ROM/Flash address space without changing the contents of the ROM/Flash itself. This function is useful if faulty parts of software or data are detected after the ROM code has been cast into mask ROM. An application software in ROM has to be prepared to support patching. It loads addresses and code or data, e.g., from external non-volatile memory to program the appropriate registers of the module. After this kind of patch module initialization, code and/or data of the specified address locations will become replaced by the contents of the patch data registers upon address matches. Single ROM locations are replaced directly. Longer, that is, faulty code sequences may be bypassed by introducing a jump-to-a-code sequence or a call of a subroutine in RAM. The program part in RAM ends with a return or jump to the appropriate address in ROM. With it, even complex software parts may be replaced. Features - patching of up to 10 different (32-bit) words in ROM address space 8-bit I/O bus 8 PAR 21 A<22:2> 1) = 21 PSELx Patch Cell x PMEN 1) Addresses refer to ROM base addr., i.e., patched ROM addr. 0x0000.0348 is 0x0020.0348 with CR.MAP = 00. PDR 32 & from other patch cells 32 PATOE data bus & from other patch cells from memory controller 1 & Patch Timing Logic & fBUS predecrom read ROM enable Fig. 10-1: Block diagram 10.1. Principle of Operation 10.1.1. General The logic contains up to ten patch cells (see Fig. 10-1 on page 89), each consisting of a 21-bit compare register (patch address register (PAR)), a 21-bit address comparator, a patch select bit (PSELx) in the patch enable register (PER) and a 32-bit patch data register (PDR). The current address information for a ROM access is fed to a bank of patch cells. In case of a match in one patch cell, and provided that the corresponding patch enable register bit is set, the module's logic disables the ROM data bus drivers and instead places the data information from the corresponding patch data register on the data bus. 10.1.2. Initialization After reset bit PER.PMEN is reset to 0 and patch operation is disabled. All patch cell registers are in write mode and may be programmed. At first, select a cell by setting the corresponding PSELx bit in register PER (PSELx = 1). Then feed the address into register PAR and the accessory 32-bit patch data into register PDR. If desired, repeat the above sequence for further patch cells. Make sure to have only one PSELx bit set at a time, although more than one register may be selected and programmed with a single access. This is possible because of used subaddressing for the address and data registers, but is probably of very rare use indeed. Micronas Feb. 10, 2005; 6251-579-1DS 89 CDC 32xxG-C 10.1.3. Patch Operation To activate a number of properly initialized patch cells for ROM code patching, set all the corresponding PSELx bits in registers PER and set bit PER.PMEN to 1 at last. The memory patch module will immediately start comparing the current address to the setting of the enabled patch cells. In case of a match the ROM data will be replaced by the corresponding patch cell data register setting. If several PDRs have been initialized with different data but same PAR contents, the patch result is unpredictable. DATA SHEET Patched data can not be observed externally on the trace bus because the patch module would deliver the gating signal too late for the logic to respond accordingly. Use the ETM to trace instead. 10.1.4. Reconfiguration To reconfigure the memory patch module, first set PER.PMEN to 0. The module will immediately terminate patch operation. Then proceed as described in 10.1.2. on page 89. 10.2. Registers PAR 7 w w w w x x Patch Address Register 6 x PER 2 x Patch Enable Register 6 x x x PSEL5 5 x 4 x 3 x A22 to A16 1 x 0 x Offs 3 2 1 w w w w 7 x x x PSEL6 5 x x x PSEL4 4 x x x PSEL3 3 x x x PSEL2 2 x x PSEL9 PSEL1 1 x x PSEL8 PSEL0 0 x x PSEL7 PMEN Offs A15 to A8 A7 to A2 0x00FFFFFF x x 0 Res 0x0000 Res PDR 7 w w w w Patch Data Register 6 5 4 3 2 1 0 Offs 3 2 1 0 Res D31 to D24 D23 to D16 D15 to D8 D7 to D0 0x00000000 PSEL0 to 9 Patch Cell Select w1: select cell for write or enabled for patch w0: de-select cell for write or disable for patch Before writing compare address or replace data of a patch cell, only one cell must be selected. In compare mode one or more patch cells can be selected. PMEN w1: w0: Patch Mode Enable enable patch mode of all cells enable write mode of all cells ICs which are derived from the Emulator IC may have less patch cells. In these cases use always cells upwards from cell 0. 90 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 11. IRQ Interrupt Controller Unit (ICU) The interrupt controller unit (ICU) manages up to 63 interrupt sources. Each interrupt source has its own interrupt vector pointing to an interrupt service routine. One of 16 priorities can be assigned to each channel, or it can be disabled. The interrupt controller unit is connected to the nIRQ input of the CPU. Features - Expanding nIRQ input of ARM7TDMI - Up to 63 interrupt sources (39 implemented) - 16 priority levels - HW vectoring - Vector table switching - HW prioritizing - HW stacking of priority levels - 2 cycles maximum from input to CPU nIRQ 11.1. Functional Description IntSrc IntSrc IntSrc IRQ: PC = 0x00000018 IAck <- Read from address [VTB] IExit <- Write to address [VTB]+0x100 Int. Src. Node EP src prio. level ISN ISN prio Priority Encoder src# 6 IExit IAck Act. Prio. Level act. prio. a 4 a>b CRI.GE & nIRQ Vect. Tab. Base 24 CRI.TE Address Bus from CPU 24 Vector Table Logic 4 b force prio 24 Address Bus to Mem. Ctrl. LDR PC,[PC,#<12_bit_offset>] LDR PC,[VTB] Fig. 11-1: Block diagram The interrupt controller unit (ICU) is composed of an interrupt source node (ISN) for each interrupt source, of a priority encoder, of a vector table logic, of an active priority level logic and a comparator (Fig. 11-1). Each falling edge of an interrupt source signals an interrupt request to its ISN and sets its pending flag "P" (Fig. 11-2). Apart from the flag P, each ISN consists of an enable flag (E), and a source priority register containing the priority of the corresponding interrupt source. As long as both flags (E and P) are true, the ISN outputs its priority. Otherwise it outputs the lowest priority (that is no priority). The priority encoder outputs number and priority of the ISN with the highest active priority. If several ISNs with the same priority are active at the same time, the ISN with the lowest source number is selected, thus the ISNs are operated in a HW-defined order. The interrupt vector table contains the start addresses of the interrupt service routines (ISR). The vector table base register points to the first entry of the interrupt vector table. Thus the location of the interrupt vector table is programmable to any memory location. This allows easy switching between different tables. DB IntSrc DB IAck src# & 6 DQ SQ D R E P & src prio level 4 to Priority Encoder Fig. 11-2: ISN flags Micronas Feb. 10, 2005; 6251-579-1DS 91 CDC 32xxG-C The active priority level logic outputs the priority of the currently running task (lowest priority is the background task). The comparator activates its output, if this priority is lower than the priority output from the priority encoder. If the ICU's output is enabled by the global enable flag (GE) the nIRQ input of the CPU is activated and held active until acknowledged. The IRQ is granted by the CPU as soon as the CPU internal IRQ flag (flag I in CPU register CPSR) is enabled by SW. In the meantime, between interrupt activation in the ICU and granting by the CPU, higher priority interrupt requests may be signaled to the ICU, raising the priority output of the priority encoder. The SW has to read the address where the vector table base register points to ([VTB]) in order to get the start address of the ISR for the ISN with the currently highest active priority (Fig. 11-3). A data fetch from this location generates an internal interrupt acknowledge signal (IAck). With IAck the active priority level logic accepts the new priority and internally saves the priority of the interrupted task. IAck clears the P flag in the corresponding ISN and deactivates the nIRQ output. The outputs of the priority encoder (registers PEPRIO and PESRC) change their values immediately and show source number and priority of the next pending interrupt. The ICU is ready for new interrupts now. Before leaving the interrupt service routine, the SW has to write to the address where VTB points to plus 0x100 ([VTB]+0x100). A write to this location generates an internal interrupt exit signal (IExit). With IExit the active priority level logic internally deletes the priority of the current task and outputs the priority of the interrupted task where the immediately following return instruction jumps to. DATA SHEET In addition to the ISNs whose inputs are connected to a HW module, some ISNs are necessary whose inputs are not connected or unused. Those interrupts can be activated by SW solely (delayed interrupt). The output of the active priority level logic may be forced by writing a higher priority to the forced priority register. This allows temporary raising of the priority of the currently running task. Writing the maximum priority to the forced priority register is another way to disable the ICU because no ISN can generate an IRQ. Raising of the priority in this way does not take effect as long as nIRQ is active. The global enable (GE) signal at the output of the comparator disables the ICU output. It is impossible to inactivate an active nIRQ output by modifying an ISN, the GE flag or forcing the priority. Only IAck resets the nIRQ output. The size of the ICU can be scaled in steps of 8 ISNs. This IC has 40 interrupt source nodes implemented (ISN0 to ISN39). Derived parts can contain 40, 32 (ISN0 to ISN31), 24 (ISN0 to ISN23) or less ISNs. The pending flags P in the ISNs operate even when the ICU is disabled (CRI.GE = 0). To be exact, only the ICU output is disabled. This avoids further interrupts. Interrupted ISRs will be finished and the Act. Prio. Level stack will be handled properly if those ISRs generate IExit before returning. SR1.IRQ reset RQ CRI.GE RQ reset CRI, AFP, ISN and internal logic disable nIRQ 100 0FC 0F8 0F4 0F0 Exit ISN63 ISR ISN62 ISR ISN61 ISR ISN60 ISR interrupt exit address Fig. 11-4: Reset structure Figure 11-4 shows the reset structure. Registers can't be written until the IRQ flag in the standby register SR1 is set. The pending flags P in the ISNs are not reset by the standby register. It can be operated by HW even while SR1.IRQ is zero. Reading and writing of the P flags is impossible unless SR1.IRQ is set to one. source number 00C 008 004 000 ISN2 ISR ISN2 ISR ISN1 ISR ISN0 ISR 32 Bit interrupt entry address Vector Table Base Fig. 11-3: Interrupt vector table Each ISN has a dedicated source number. A maximum of 64 ISNs can be connected to the priority encoder. The priority encoder outputs source number 0 as long as all ISNs output priority 0 or no ISN is active or the comparator output is inactive. This is to guarantee a valid state of the priority encoder and return a valid start address even if no interrupt source is active. The corresponding vector is the first in the vector table (default vector). For this reason ISN0 can't be used for connecting an interrupt source, because ISN0 is not the only user of the corresponding interrupt vector. For example, reading the address location pointed to by the vector table base register while nIRQ is inactive, will return the ISR start address of ISN0. 92 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Table 11-1: Interrupt assignment ISN 32 33 34 35 36 37 38 39 Interrupt Source CAN3 CAN2 CC0COMP CC1COMP CC2COMP CC3COMP PINT4 GBus Table 11-1: Interrupt assignment ISN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Interrupt Source Default vector, not connected CC0OR CC1OR PINT0 PINT1 CAN0 SPI0 Timer 1 Timer 0 P06 COMP RESET/ALARM WAIT COMP UART0 PINT2 WAPI CC2OR CC3OR Timer 2 RTC I2C0 Timer 3 SPI1 COMMRX (buffer not empty) ored with COMMTX (buffer empty) PINT5 PINT3 DIGITbus I2C1 CAN1 CC4OR CC5OR Timer 4 UART1 Micronas Feb. 10, 2005; 6251-579-1DS 93 CDC 32xxG-C 11.2. Timing DATA SHEET CPU fSYS (ECLK) IntSrc prio comp nIRQ src# Fig. 11-5: Timing The sample period of an incoming interrupt request lasts one cycle in the worst case. It is sampled by an ISN with the falling edge of fSYS. Priority Encoder and comparator require another cycle. The CPU finally evaluates with the next falling edge of fSYS. This results in a maximum delay of 2 fSYS cycles from request to CPU input. 11.3. Registers FPRIO Forced Priority r/w: (Table 11-3) Writing a value higher than the APRIO value to this location raises the priority of the actual running ISR. It doesn't change APRIO. Only ISRs with a priority higher than the forced priority are able to interrupt now. Res CRI 7 r/w GE 0 Control Register IRQ 6 TE 0 5 x x 4 x x 3 x x 2 x x 1 x x 0 x x GE Global Enable r/w1: Enable IRQ. r/w0: Disable IRQ. Disabling happens as soon as nIRQ is inactive. An active nIRQ will not be interrupted by writing a zero to GE. TE Table Enable r/w1: Enable. r/w0: Disable. The Vector Table Logic doesn't work if TE is disabled. Neither the correct ISR start address is returned nor the internal signals IAck and IExit are generated on accessing the dedicated memory location. It is necessary to first save the original FPRIO value before raising the own priority by overwriting FPRIO. The saved FPRIO value has to be restored before ISR exit. PEPRIO 7 r x x Priority Encoder Priority output 6 x x 5 x x 4 x x 3 2 Priority 1 0 0 0 0 0 Res This register shows the priority of the highest pending and enabled interrupt source. AFP 7 r/w 0 0 Actual and Forced Priority Register 6 APRIO 0 0 0 0 PESRC 7 r x x Priority Encoder Source output 6 x x 0 0 0 5 4 3 2 FPRIO 1 0 5 4 3 Source 2 1 0 0 0 Res 0 0 0 Res APRIO Actual Priority r: (Table 11-3) This field indicates the programmed priority of the actually running ISR. It is modified by HW only. This register shows the number of the highest pending and enabled interrupt source. 94 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C this interrupt source node is enabled, this flag is cleared by HW as soon as the corresponding ISR is called. 2 0 VTB 7 r/w r/w r/w r/w 0 0 0 Vector Table Base 6 0 5 0 4 0 3 0 1 0 0 0 3 Offs Table 11-2: Pending flag access M P 0 1 0 1 Read Not pending Pending Not possible Clear P Set P Write Don't modify P Address bit 23 to 16 Address bit 15 to 9 0 0 0 0 0 0 0 2 1 0 Res 0 0 1 1 0x00000000 The register VTB has to be programmed with the memory base address of the interrupt vector table. The interrupt vector table has to start at an even page address (9 LSB are zero) and is not longer than one page (256 bytes). Apart from the start address of the interrupt vector table, VTB defines two addresses which perform HW actions when accessed and CRI.TE is set. Every word read access to the location addressed by VTB deactivates the nIRQ output. If the comparator output is active, the internal signal IAck is activated, which returns the ISR start address of the ISN with the highest active priority, clears the corresponding P flag and saves the interrupted priority. Every word write access to the location addressed by VTB plus 0x100 activates the internal signal IExit. Accessing these locations ([VTB] and [VTB]+0x100) without generating IAck or IExit is possible when the vector table logic is disabled (CRI.TE = 0). E Enable r/w1: Enable interrupt. r/w0: Disable interrupt. This flag is modified by SW only. PRIO Interrupt Source Node Priority This field is modified by SW only (Table 11-3). Table 11-3: Priority encoding PRIO 3 0 0 0 2 0 0 0 : 1 1 1 0 0 1 : 1 1 0 0 1 0 : 0 1 0 (No priority) 1 (Lowest priority) 2 : 14 15 (Highest priority) Priority number ISNx 7 r/w M 0 Interrupt Source Node Register x 6 P x : 1 1 5 E 0 4 x x 3 2 PRIO 1 0 0 0 0 0 Res M Modify Pending Flag (Table 11-2) w1: Modify Pending flag. r/w0: Don't modify Pending flag. This flag is modified by SW only and always reads as 0. It allows modification of register ISNx without influence to flag P. Without this flag a HW modification of flag P could be corrupted by a simultaneous read-modify-write of register ISNx. P Pending (Table 11-2) r/w1: Interrupt is pending. r/w0: No interrupt pending. This flag can be modified by HW and SW. It is set by HW when the corresponding interrupt source input is activated. If Micronas Feb. 10, 2005; 6251-579-1DS 95 CDC 32xxG-C 11.4. Principle of Operation 11.4.1. Reset Clearing standby register flag SR1.IRQ resets the ICU (see Fig. 11-4 on page 92). The registers are reset to their mentioned values (see Section 11.3. on page 94) and cannot be modified. The nIRQ output is inactive and the actual priority level logic is cleared. DATA SHEET vector table has to be located within 4 kB from the above instruction. Above instruction is called vectoring. There are two possibilities for the point of time, direct and delayed, when vectoring takes place. 11.4.3.1. Direct Vectoring Above instruction is the first instruction which is executed when an interrupt occurs. The address 0x18 contains the PC relative load PC instruction. 11.4.3.2. Delayed Vectoring Above instruction is delayed. The address 0x18 contains a jump to a short piece of code which does all that has to be done for every ISR (save LR, SPSR and working registers). After this common prefix, the jump to the appropriate ISR is launched by the PC relative load PC instruction. 11.4.2. Initialization Proper configuration of the interrupt sources in the peripheral modules has to be made prior to initialization of the ICU. Initialization is possible after the standby register flag SR1.IRQ has been written to one. Now the registers can be modified by SW. But no interrupt request is generated to the CPU. Install the vector table beginning at an even page address (9 LSB are zero). Each entry has to be a 32-bit start address of an interrupt service routine. The vector table has to be located near (4 kB) the load PC instruction. Write the start address of the vector table to the vector table base register VTB. Further access to register VTB is not necessary until you want to switch to another vector table at another location. Set up the interrupt source node registers ISNx with the necessary priority and enable them. The pending flags have to be cleared, because they are not cleared by SR1.IRQ and are operative all the time. Clearing an active pending flag and enabling the corresponding ISN must not be done with a single instruction. This might lead to an unwanted (spurious) interrupt which is directed to the default vector. First clear P and then set E in two instructions. Interrupt sources which shall not generate interrupts must not be enabled and need no priority (PRIO=0), but can be operated by polling and resetting the pending flag P by SW. 11.4.4. CPU Mode Switching A CPU mode switch (see Section 4.2. on page 39) has to be handled like critical code. Disable the ICU prior to the mode switch by setting CPSR flag I of the ARM core (see Section 11.5.7.1. on page 97) or by clearing flag CRI.GE (see Section 11.5.7.2. on page 98). The ICU can be enabled again after the CPU mode switch sequence has finished. If the mode switch has to be done within an ISR, wait with the generation of the signal IExit until the ICU has been enabled again. 11.4.5. Inactivation An interrupt source can be disabled locally by clearing the enable flag E in the corresponding ISN register. Even a pending interrupt can be disabled this way. A disabled ISN does not participate in sending interrupt requests to the CPU. All interrupt sources can be disabled globally by clearing the global enable flag CRI.GE. It is impossible to inactivate an active nIRQ output signal by clearing CRI.GE. An active nIRQ will be served and only further IRQs can be suppressed by setting the GE flag. The pending flag P stays operative in both cases and may be polled by SW. A zero in the standby register flag SR1.IRQ immediately resets registers and logic and forces the nIRQ output to become inactive. 11.4.3. Operation The ICU is operable in all CPU modes. However, interrupts have to be disabled during CPU mode switching to prevent undefined clock system behavior. Setting both flags CRI.GE and CRI.TE enables the ICU at last. When an interrupt occurs, execution starts at address 0x18. For proper operation of the ICU the jump to the interrupt service routine has to be done by the PC relative load PC instruction LDR PC,[PC,#<12_bit_offset>], where the operand [PC,#<12_bit_offset>] must point to the first entry of the vector table. Due to the 12_bit_offset the 11.5. Application Hints 11.5.1. Hardware Triggered Interrupts Normally, the connected peripheral modules set the pending flag P. If the ISN is enabled (E=1) and the priority is not zero, an IRQ is generated. The P flag will be reset as soon as the corresponding interrupt service routine is called. It is not required and should be avoided to modify the P flag of those ISNs by SW. 11.5.2. Software Triggered Interrupts Any ISN which is not used by the connected peripheral module can be used for generating IRQ interrupts by SW. It must be avoided that the interrupt source of this ISN also generates interrupt requests. Either the corresponding peripheral module has to be switched off, or its interrupt source output has to be disabled. 96 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C PC,R14_irq,#4). The ISN has to be enabled (E=1) and programmed to the desired priority (PRIO>0). Setting the pending flag P by SW generates an interrupt. This interrupt will be processed as soon as possible. When the CPU responds to the interrupt request and jumps to the corresponding ISR, the pending flag is cleared automatically. 11.5.2.1. Delayed Interrupt Any ISN which is not used by the connected peripheral module can be used for implementing the delayed interrupt mechanism for an operating system. The ISN has to be enabled (E=1) and programmed to priority 1 (the lowest priority which can generate an interrupt). Setting the pending flag P by OS-SW within a higher priority interrupt service routine generates a delayed interrupt, which is processed after all higher priority interrupts are finished. 11.5.5. Default Vector Any read access to vector table address [VTB] will deliver the default vector, but will not generate IAck as long as the comparator output is inactive or the priority output of the priority encoder is zero. Due to this the default vector ISR runs with the priority of the interrupted routine. This is the only ISR which could be interrupted by itself. As long as this default vector ISR is not programmed re-entrant, interrupts should not be re-enabled by clearing the I flag of the CPSR. No IExit shall be generated on interrupt exit by writing to [VTB]+0x100 because there was no IAck at interrupt entry. Unintentional inactivation of an active comparator output signal can be caused by modifying the ISN which is the only source for the momentary active nIRQ output. This can be done by disabling (E=0), or clearing the P flag, or lowering the priority of this ISN. These actions may lead to a default vector interrupt. 11.5.3. Polling Polling means that the pending flag P is observed by SW. Set by the corresponding interrupt source, the SW recognizes the P flag to be set, calls the corresponding routine and clears the P flag. The ISN should be disabled (E=0), otherwise unwanted IRQs would be generated. 11.5.6. Debugger Unintentional access to vector table addresses [VTB] and [VTB]+0x100 can result in malfunction of the interrupt system (HW and SW). If it is necessary, for instance, to dump the vector table, there are two ways to do this without generation of IAck or IExit: The first way is to clear the flag CRI.TE which controls the vector table logic. Clearing it disables HW actions on accessing above addresses. But ensure that no interrupts are possible while TE is disabled. The second way is to access above addresses by byte or half word operations only. The HW actions are only generated by word access. Disabling interrupts is not required in the latter case. 11.5.4. Operating Nested Interrupts Nested interrupt service routines use common data resources. Every routine, which may have interrupted a lower priority routine, has to save common data resources upon interrupt entry and restore them before returning to the interrupted routine. This is efficiently done by an entry and an exit sequence which are enclosing the interrupt service routine. 11.5.4.1. Interrupt Entry Sequence The IRQ disable flag I in the core register CPSR is set after an IRQ, thus disabling further IRQs. Before the interrupt is enabled again, the user has to take the following steps: 1. For direct vectoring: Jump to the corresponding interrupt service routine by loading the first element from the vector table into the program counter by an LDR instruction. 2. Save Link Register (R14), SPSR and working registers to stack. 3. For delayed vectoring: Jump to the corresponding interrupt service routine by loading the first element from the vector table into the program counter an LDR instruction. 4. Clear CPSR.I to re-enable IRQs. Now the actual application ISR can start. 11.5.4.2. Interrupt Exit Sequence Before returning, it is necessary to clear the interrupt cause. Upon exit from an ISR some actions have to be taken without being interrupted: 1. Set CPSR.I to disable further IRQs. 2. Restore link register (R14), SPSR and working registers from stack. 3. Generate the signal IExit by performing a word write by an STR instruction to the interrupt exit address at [VTB]+0x100. 4. Returning to the interrupted routine has to be done by an instruction, which simultaneously writes the PC (R15) and CPSR with the values in R14 and SPSR (e.g., SUBS 11.5.7. Critical Code Critical code is a sequence of instructions which must not be interrupted, because it modifies common data resources. Protection from being interrupted can be achieved by disabling interrupts during critical code. There are several ways of doing this: 11.5.7.1. ARM Core's Interrupt Disable Flag I and F The ARM core itself provides the interrupt disable bits I and F in the program status register CPSR. The control bits of the CPSR (I, F and others) can be SW altered only when the processor is in a privileged mode. ARM recommends to modify the CPSR by a read-modifywrite instruction sequence in order to leave the reserved bits unchanged. MRS ORR MSR r0,cpsr r0,r0,#I_Bit cpsr_c,r0 ;disable interrupts The interesting case is when an interrupt comes in during execution of the MSR instruction. The core commits to taking an interrupt before the instruction being executed completes. Therefore even though an MSR instruction may have written to the CPSR to disable interrupts, the interrupt will still be taken. A NOP between the MSR instruction and the first instruction of the critical code is not necessary. If an interrupt Micronas Feb. 10, 2005; 6251-579-1DS 97 CDC 32xxG-C occurs during an MSR instruction, it will return to the instruction immediately following the MSR. 11.5.7.2. Global Enable Flag GE Protection of critical code can be achieved by disabling the nIRQ output with the global enable flag CRI.GE. The GE flag changes its value in the cycle after the data transfer of the store instruction. In this cycle the next instruction is in the execution stage of the CPU and will be executed. Due to this, one NOP is required between the store instruction, which clears CRI.GE, and the first instruction of the critical code. 11.5.7.3. Force Priority To protect critical code, further IRQ interrupts can be disabled by writing the maximum priority to the forced priority register AFP. Modifying AFP works like clearing the GE flag. One NOP is required between the store instruction, which writes AFP, and the first instruction of the critical code. 11.5.7.4. Disabling via ISN At last, critical code protection can be achieved by disabling all ISNs by clearing their enable flag E. The priority encoder is calculated at the beginning of a cycle. Due to this, changing an ISN register becomes effective only in the next cycle. Two NOPs are required between the store instruction, which clears the flag E, and the first instruction of the critical code. DATA SHEET 11.5.8. Switching an Interrupt Vector Interrupt service routines of an interrupt source can easily be changed by entering the start address of the new ISR at the corresponding entry of the interrupt vector table. 11.5.9. Switching the Vector Table Switching between different vector tables is possible if they have been installed. Changing the vector table is simply done by writing the base address of the new vector table to register VTB. All subsequent interrupt service routines must relate to this vector table. Due to this, it is necessary for an ISR in such an environment to read the location of the current vector table from register VTB before accessing it. Be careful when switching vector tables within an ISR. Interrupted ISRs could try to do the IExit from an outdated table. 98 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 12. FIQ Interrupt Logic The FIQ interrupt logic selects one out of eight interrupt sources as the CPU's nFIQ input. An interrupt request is latched in a pending flag until it is cleared by SW. The output can be disabled. Features - Expanding nFIQ input of ARM7TDMI - 1 of 8 selection - IRQ or FIQ selectable 12.1. Functional Description CRF.SEL Interrupt Sources FIQ0 FIQ1 FIQ2 FIQ3 FIQ4 FIQ5 FIQ6 FIQ7 0 1 DB 1 DB DQ SQ D CRF.GE CRF.P & nFIQ to ISNs Fig. 12-1: Block diagram FIQ At one time, only one interrupt source can be connected to the nFIQ input of the CPU. The interrupt source which is connected to the nFIQ, is disconnected from the corresponding ISN. This ISN can then be used by SW. reset SR1.FIQ RQ reset CRF Fig. 12-2: Reset structure Figure 12-2 shows the reset structure. Registers can't be written until the FIQ flag in the standby register SR1 is set. 12.2. Registers This flag is set by HW and SW. It must be cleared by SW before re-enabling FIQ by bit F in the core's CPSR register, or no further interrupt can occur. 1 x x PRF 7 r/w x x Pending Register FIQ 6 x x 5 x x 4 x x 3 x x 2 x x 0 P CRF 0 Res Control Register FIQ 6 x x 7 5 x x 4 x x 3 2 SEL 1 0 P r/w1: r/w0: FIQ Pending Pending FIQ. No pending FIQ. r/w GE 0 0 0 0 0 Res Micronas Feb. 10, 2005; 6251-579-1DS 99 CDC 32xxG-C GE Global Enable FIQ r/w1: Enable FIQ. r/w0: Disable FIQ. Disabling happens as soon as nFIQ is inactive. An active nFIQ will not be interrupted by clearing GE. SEL r/w: Select FIQ Source (Table 12-1) DATA SHEET Table 12-1: FIQ source selection SEL 3 0 1 1 1 1 1 1 1 1 2 x 0 0 0 0 1 1 1 1 1 x 0 0 1 1 0 0 1 1 0 x 0 1 0 1 0 1 0 1 Switched to nFIQ Select None FIQ0 FIQ1 FIQ2 FIQ3 FIQ4 FIQ5 FIQ6 FIQ7 6 11 12 13 15 17 19 5 SPI0 WAIT COMP UART0 PINT2 CC2OR Timer 2 I2C0 CAN0 ISN Interrupt Source 12.3. Principle of Operation 12.3.1. Reset Clearing standby register flag SR1.FIQ resets the FIQ interrupt logic (see Fig. 12-2 on page 99). The registers are reset to their mentioned values (see Section 12.2. on page 99) and cannot be modified. The nFIQ output is inactive. 12.3.2. Initialization Proper configuration of the interrupt sources in the peripheral modules has to be made prior to initialization of the FIQ interrupt logic. Initialization is possible after the standby register flag SR1.FIQ has been set. Now the registers can be modified by SW. But no interrupt request is generated to the CPU. The FIQ interrupt logic is operable in all CPU speed modes. 12.3.3. Operation Setting flag CRF.GE enables the FIQ interrupt logic. When an interrupt occurs, execution starts from address 0x1C. 12.3.4. Inactivation The FIQ interrupt logic can be disabled by clearing the global enable flag CRF.GE. An active nFIQ will be served, however, and only future FIQs will be suppressed by clearing the GE flag. Clearing the standby register flag SR1.FIQ immediately resets registers and logic and forces the nFIQ output to become inactive. 100 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 13. Port Interrupts Port interrupts are the interface of the interrupt controller to the external world. Six U-port pins and, alternatively, six Pport pins are connected to the module via their special input lines (Fig. 13-1). HW-Option-programmable multiplexers define which port signal is actually connected to the trigger mode logic (Table 13-1). The P-ports are actually analog input ports, thus Schmitt triggers are enabled if the P-ports are selected as port interrupts. The input sampling frequency is f0perm, which is not disabled by CPU SLOW or DEEP SLOW modes. trigger input circuit is enabled. This is the reason why input levels other than AVDD and AVSS may cause quiescent currents in the Schmitt trigger circuit and thus lead to higher power consumption. Table 13-1: Module-specific settings Module Name PINT0 HW Options Item Port Multiplexers Initialization Address Item Setting HW Option PM.PINT 0 U1.7 1 P1.2 f0perm PINT0 PM.PINT PINT0 U1.7 special in P1.2 IRPM0 PINT0 Interrupt Source PINT1 PINT1 PINT1 Interrupt Source PINT1 U1.6 special in P1.3 U1.6 PINT2 PINT2 U1.5 special in P1.4 P1.3 PINT2 Trigger Mode U1.5 PINT2 Interrupt Source PINT3 PINT3 U8.5 special in P1.5 P1.4 PINT4 U8.5 PINT3 PINT3 Interrupt Source PINT4 U0.5 special in P1.6 P1.5 PINT4 PINT5 PINT5 U0.4 special in P1.7 U0.5 IRPM1 Trigger Mode PINT4 Interrupt Source P1.6 PINT5 IRPM0 7 6 PIT3 0 0 Interrupt Port Mode Register 0 5 PIT2 0 0 0 4 3 PIT1 2 1 PIT0 0 U0.4 PINT5 Interrupt Source r/w 0 0 0 Res P1.7 Fig. 13-1: Port interrupts The user can define the trigger mode for each port interrupt by the interrupt port mode register. The trigger mode defines on which edge of the interrupt source signal the Interrupt Controller is triggered. The triggering of the interrupt controller is shown in figure 13-2. For the effect of CPU clock modes on the operation of this module refer to section "CPU and Clock System" (see Table 4-1 on page 41). Precautions Parallel usage of a P-port as analog and port interrupt input is possible but not recommended. In this case the Schmitt IRPM1 7 r/w x x Interrupt Port Mode Register 1 6 x x 5 x x 4 x x 3 PIT5 0 2 1 PIT4 0 0 0 0 Res Micronas Feb. 10, 2005; 6251-579-1DS 101 CDC 32xxG-C PITn Port interrupt trigger number n This field defines the trigger behavior of the associated port interrupt (Table 13-2). DATA SHEET Table 13-2: PITn usage PITn 0h 1h 2h 3h Trigger Mode Interrupt source is disabled Rising edge Falling edge Rising and falling edges Port input Interrupt (low active) Interrupt (low active) Interrupt (low active) Fig. 13-2: Interrupt timing Falling edge Rising edge Falling and rising edge trigger mode 102 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 14. Ports This chapter describes the P-, U- and H-Ports. The analog input ports, P0 and P1, serve as input for the analog-to-digital converter and may be used as digital inputs. P2 may be used as digital input, only. The universal ports U0 to U8 serve as digital I/O and can be configured as LCD drivers. The high current ports H0 to H7 serve as digital I/O and can be configured as stepper motor drivers. 14.1. Analog Input Port The 16-pin analog input port is composed of ports P0 and P1. All port pins can be configured as digital input. P0.6 is connected to a comparator, which may be selected as interrupt source. P1.2 to P1.7 can be used as port interrupts. The 2-pin port P2 solely serves as digital input. Features - 16-pin analog input multiplexer. - 18 pins configurable as digital input ports. - Schmitt hysteresis digital input buffer, CMOS level (2.5 V) or automotive level (3.3 V) selectable. - 6 pins configurable as port interrupts. - 2 pins usable as wake-up input. P0.0 to P0.7 P1.0 to P1.7 P2.0 to P2.1 8 8 2 18 8 8 16:1 MUX P0.6 to Alarm Comparator To A/D converter 2 P1.0 to P1.1 to Port Wake logic (wake in) P1.2 to P1.7 to port interrupts 0 to 5 PxPIN.Py AVDD VDD 6 PxLVL.Ay PxIE.Iy rd Fig. 14-1: P-Ports with input multiplexer and P0.6 alarm comparator P0 and P1 analog input lines are connected to a multiplexer. The output of this multiplexer is connected to the 10-bit A/D converter. Port P0.6 is, in addition, the input of the P0.6 alarm comparator, described in the chapter on the analog section. P0 and P1 pins may alternatively, P2 may exclusively be used as digital input if enabled by setting the individual pin's enable flag PxIE.Iy. CMOS or automotive Schmitt trigger input level may individually be selected by writing registers PxLVL. The digital value of the input pins is obtained by reading registers PxPIN. Disabled inputs read as 1. Pins should either be used as analog or digital inputs, not both at the same time. Six of the analog input pins (P1.2 to P1.7) may be used as port interrupt input if selected by HW Option PM.PINT (see sections "Port Interrupts" and "HW Options" for more details). Configure as digital input for this operation. Ports P1.0 and P1.1 may be used as wake-up inputs (see section "Power Saving Module" for details), hence their digital input enable flags (P1IE.I0 and I1) reset to 1 (input buffer enabled). PxPIN 7 r P7 1 Port x Pin Register 6 P6 1 5 P5 1 4 P4 1 3 P3 1 2 P2 1 1 P1 1 0 P0 1 Res P0 to 7 r: Pin Data 0 to 7 Read Pin state PxLVL 7 r/w A7 0 Port x Input Level Register 6 A6 0 5 A5 0 4 A4 0 3 A3 0 2 A2 0 1 A1 0 0 A0 0 Res A0 to 7 r/w1: r/w0: Automotive Flag 0 to 7 Schmitt trigger input level is Automotive Schmitt trigger input level is CMOS Micronas Feb. 10, 2005; 6251-579-1DS 103 CDC 32xxG-C DATA SHEET P0IE 7 r/w I7 0 I Port 0 Input Enable Register 6 I6 0 5 I5 0 4 I4 0 3 I3 0 2 I2 0 1 I1 0 0 I0 0 Res I0 to 7 r/w1: r/w0: Digital Input Enable 0 to 7 Enable input buffer Disable input buffer P1IE 7 r/w I7 0 I Port 1 Input Enable Register 6 I6 0 5 I5 0 4 I4 0 3 I3 0 2 I2 0 1 I1 1 0 I0 1 Res I0 to 7 r/w1: r/w0: Digital Input Enable 0 to 7 Enable input buffer Disable input buffer P2IE 7 r/w x Port 2 Input Enable Register 6 x 5 x 4 x 3 x 2 x 1 I1 0 0 I0 0 Res I I0 to 1 r/w1: r/w0: Digital Input Enable 0 to 1 Enable input buffer Disable input buffer 104 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 14.2. Universal Ports U0 to U8 Universal ports are pin-configurable as SW I/O port, special input/output port (SI/SO) to special internal hardware modules or direct drive of 4:1 multiplexed LCD segment and backplane lines (LCD port). The output drivers feature a current fold-back characteristic to allow shorting the output and to improve EMI performance. Features - Pin-configurable as I/O or Special Port or LCD driver. - LCD mode: 1-to-4 multiplex, 5 V supply. - PORT mode: push-pull or open-drain output. - Two output current fold-back characteristics selectable - Schmitt hysteresis input buffer, CMOS level (2.5 V) or automotive level (3.3 V) selectable. UxMODE.Ly wake in Special In UxPIN.Py UxLVL.Cy UxSLOW.Sy UxTRI.Ty UxD.Dy Special Out UxNS.Sy From LCD UxDPM.Dy UVDD UVSS UVDD 0 1 & Current Fold Back Current Fold Back UVSS 0 1 Ux.y 1 MUX Analog Switch and Segment Driver 2 1 /3UVDD /3UVDD x: Port number 0 to 8 y: Port pin number 0 to 7 Fig. 14-2: Universal port pin circuit diagram The universal port pins can be configured for several basic operating modes (Table 14-1) Table 14-1: Universal port basic operating modes Modes Port Mode Normal Input Special Input Normal Output Special Output LCD Mode Function The SW uses the port as digital input. The port input is additionally connected to specific hardware modules. The SW uses the port as latched digital tristateable output. The output signals of specific hardware modules are directly port output source. The port pin serves as backplane/segment driver for a 4:1 multiplexed LC display After reset, all universal ports are in port, normal, tristate, CMOS input level condition. SLOW mode is disabled. See the chapter on pinning for information about specific hardware module connections to individual port pins for special input and special output purposes. Universal port control is distributed among eight registers. Four of these registers have duplicate functions for port and LCD mode. All register bits corresponding to one U-Port pin are controlled by the same bus bit. In both LCD and Port modes, the SLOW mode may be defined for each individual U-Port pin. It reduces the current drive capability of the output stage. Set flag SR0.PSLW to enable this operation mode. 14.2.1. Port Mode For port mode, the respective UxMODE register bit has to be cleared for mode selection. Micronas Feb. 10, 2005; 6251-579-1DS 105 CDC 32xxG-C The function of the seven remaining registers is given in Table 14-2. DATA SHEET Table 14-2: Register functions in port mode Register UxD UxTRI UxNS UxDPM UxSLOW UxLVL UxPIN Function r/w data register enable/disable output select data register or specific hardware module as output source select push-pull or open-drain, double drive mode for output drivers enable/disable port slow mode for output drivers select CMOS or automotive Schmitt trigger input level read pin state The output sequence timing on backplane and segment output ports in LCD mode is controlled by the LCD module. Please refer to section LCD module for information about operation of this module. As generation of the backplane port output sequence is fully done by the LCD module, no segment line data setting is necessary for these ports. 14.2.3. Port Fast and Slow Modes Once individual port pins have been enabled for port slow mode by setting registers UxSLOW, set flag SR0.PSLW to simultaneously enter this mode in all respective ports. All U-ports exhibit two operating regions in the DC output characteristic (see Fig. 14-3). Near zero output voltage, the internal driver transistors operate non-limited, to offer a linear, low on-resistance. With larger output voltages, however, the output current folds back to a a limited value. This measure helps to fight supply current transients and related EMI noise during port switching. In the fold-back region, port fast mode and port slow mode select two different current limits Ishf and Ishs. Port slow mode sets a limit where the output may even be shorted continuously to either supply rail. Thus, wired-or configurations may be realized. The external load resistance should be greater than 5 kOhms in port slow mode. For actually switching to port slow mode, both registers UxSLOW and SR0.PSLW have to be set. In all other cases, port fast mode is selected. It is recommended to place all LCD ports in Port Slow mode. In port mode, the special input path is always operative. This allows manipulating the input signal to the specific hardware module through normal output operations by software. Because register UxPIN allows reading the pin level also in special output mode, the output state of the specific hardware module may be read by the CPU. 14.2.2. LCD Mode For LCD Mode, the respective UxMODE register bit has to be set for mode selection. The function of the seven remaining registers is given in Table 14-3. Io Nonlimited region Limited region Table 14-3: Register functions in LCD mode Register UxD UxTRI UxNS UxDPM UxSLOW UxLVL UxPIN Function r/w phase 0 segment line data r/w phase 1 segment line data r/w phase 2 segment line data r/w phase 3 segment line data enable/disable port slow mode for output drivers no function no function 0 1V 2V 3V 4V 5V Ishs Port Slow Mode Ishf Port Fast Mode By writing segment line data registers, only a master is changed. Any write to global register ULCDLD will transfer all master settings to the respective slaves and thereby change the LC display in one instant. Registers UxD, UxTRI, UxNS and UxDPM compose a wordaligned 32-bit register and may be accessed by one 32-bit operation. Vol Fig. 14-3: Typical U-Port pull-down DC output characteristic (pull-up characteristic is complementary). 106 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 14.3. Universal Port Registers Eight U-Port registers are basically available for 9 U-Ports U0 to U8, each. Because some U-Ports are less than 8 pins wide, not all of the described bits are available for every port. Furthermore, the respective device's pinning may require a reduction in available U-Ports. See the respective pinning table for details. The general U-port register model is given below. r/w SG7_2 0 SG6_2 0 SG5_2 0 SG4_2 0 SG3_2 0 SG2_2 0 SG1_2 0 SG0_2 0 LCD Res UxNS 7 r/w S7 Universal Port x Normal-Special / Segment 2 Register 6 S6 5 S5 4 S4 3 S3 2 S2 1 S1 0 S0 Port UxMODE 7 r/w L7 0 Universal Port Mode Register 6 L6 0 5 L5 0 4 L4 0 3 L3 0 2 L2 0 1 L1 0 0 L0 0 Res S0 to 7 r/w1: r/w0: Normal/Special Mode Flag 0 to 7 Special mode. Special hardware drives pin. Normal mode. Data latch drives pin. UxDPM L0 to 7 Port Mode Flag Select the mode of the corresponding port pins. r/w1: Port pin is in LCD mode. r/w0: Port pin is in Port mode. 7 r/w r/w D7 SG7_3 0 Universal Port x Double Pull-Down Mode / Segment 3 Register 6 D6 SG6_3 0 5 D5 SG5_3 0 4 D4 SG4_3 0 3 D3 SG3_3 0 2 D2 SG2_3 0 1 D1 SG1_3 0 0 D0 SG0_3 0 Port LCD Res UxD 7 r/w r/w D7 SG7_0 0 Universal Port x Data / Segment 0 Register 6 D6 SG6_0 0 5 D5 SG5_0 0 4 D4 SG4_0 0 3 D3 SG3_0 0 2 D2 SG2_0 0 1 D1 SG1_0 0 0 D0 SG0_0 0 Port LCD Res D0 to 7 r/w1: r/w0: Double Pull-Down Mode Output driver is pull-down, Ishs (Port Slow mode) doubled. Standard. All U-port pins may be switched into a double pull-down mode (DPM) by setting the appropriate DPMx flag, where - the short circuit current Ishs is doubled (with Port Slow Mode enabled for these ports, and SR0.PSLW set to 1) - the output configuration is pull-down, not the standard push-pull. By this means, these ports may be configured to operate as connection to a wired-or, single-wire bus (e.g., DIGITbus or I2C) with external pull-up resistor. D0 to 7 w: r: Data Latch Write latch. Read latch. SG0_0 to 7_3 Segment Data Latch w: Write latch. r: Read latch. In LCD mode, U-Port registers UxD, UxTRI, UxNS and UxDPM store LCD segment information. Segment register bits UxY.SGm_n contain the information for segment line m during phase n, which controls segment m_n. Thus, register bits UxD.SG0_0, UxTRI.SG0_1, UxNS.SG0_2 and UxPIN.SG0_3 contain the complete information for segment line 0 in U-Port x. Please refer to pin assignment and description for segment/ pin number assignment. Information about the usage of the LCD segment field will be found at the functional description of the LCD module. UxSLOW 7 r/w S7 0 Universal Port x Slow Mode Register 6 S6 0 5 S5 0 4 S4 0 3 S3 0 2 S2 0 1 S1 0 0 S0 0 Res S0 to 7 r/w1: r/w0: Slow Flag 0 to 7 Output driver is in Port Slow mode Output driver is in Port Fast mode UxTRI 7 r/w r/w T7 SG7_1 1 Universal Port x Tristate / Segment 1 Register 6 T6 SG6_1 1 UxLVL 7 6 A6 0 Universal Port x Input Level Register 5 A5 0 5 T5 SG5_1 1 4 T4 SG4_1 1 3 T3 SG3_1 1 2 T2 SG2_1 1 1 T1 SG1_1 1 0 4 A4 0 3 A3 0 2 A2 0 1 A1 0 0 A0 0 Res T0 SG0_1 1 Port r/w LCD 0 Res A7 T0 to 7 r/w1: r/w0: Output Tristate Flag 0 to 7 Output driver is disabled (tristate) Output driver is enabled A0 to 7 r/w1: r/w0: Automotive Flag 0 to 7 Schmitt trigger input level is Automotive Schmitt trigger input level is CMOS Micronas Feb. 10, 2005; 6251-579-1DS 107 CDC 32xxG-C DATA SHEET UxPIN 7 r P7 x Universal Port x Pin Register 6 P6 x 5 P5 x 4 P4 x 3 P3 x 2 P2 x 1 P1 x 0 P0 x Res P0 to 7 r: Pin Data 0 to 7 Read Pin state. ULCDLD 7 w LCDSLV 0 Universal Port LCD Load Register 6 x 0 5 x 0 4 x 0 3 x 0 2 x 0 1 x 0 0 x 0 Res LCDSLV LCD Module is Slave Select the mode of the LCD module. w1: LCD module is slave. w0: LCD module is master. A write access to this memory location simultaneously loads all segment information of all U-Ports in LCD mode to the display. The flag LCDSLV is available only in LCD mode. 14.3.1. Special Register Layout of U-Port 4 U4.0 to U4.3 provide backplane signals in LCD Mode. To operate any ports as LCD segment driver it is necessary to switch all these ports to LCD mode. This has to be done by setting flags U4MODE.L0 through U4MODE.L3. As backplane ports U4.0 to U4.3 require no segment data setting, SG0_0 through SG3_3 bits are not available in U4 registers. 108 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 14.4. High Current Ports H0 to H7 High current ports 0 to 7 are used to drive coils of stepper motors. All ports are 4 pins wide to facilitate control of individual stepper motors. The H-ports are similar to universal ports but as the name says, they can drive higher currents. H-ports can be operated via software just like universal ports (port mode). Their special out inputs are connected to the stepper motor module or to PWM outputs. Features - Pin-configurable as I/O or Special Port driver - 30 mA output current - Schmitt hysteresis input buffer, CMOS level (2.5 V) or automotive level (3.3 V) selectable. - Reduced slew rate of current and voltage for driving resistive, capacitive or inductive loads. HVDD Special In HxPIN.Py HxLVL.Cy HxTRI.Ty HxD.Dy Special Out HxNS.Sy 0 1 & HVSS HVDD Slew Rate Control x: Port number 0 to 7 y: Port pin number 0 to 3 Hx.y & Slew Rate Control HVSS Fig. 14-4: High current port pin circuit diagram The H-port pins can be configured for several basic operating modes (Table 14-4) The function of the five registers is given in Table 14-5. Table 14-5: Register functions Table 14-4: High current port basic operating modes Register Mode Normal Input Special Input Function HxD The SW uses the port as digital input. The port input is additionally connected to specific hardware modules. The SW uses the port as latched digital tristateable output. HxPIN Special Output The output signals of specific hardware modules are directly port output source. HxTRI HxNS HxLVL Normal Output r/w Data register enable/disable output select Data register or specific hardware module as output source select CMOS or Automotive Schmitt trigger input level read pin state Function The special input path is always operative. This allows manipulating the input signal to the specific hardware module through normal output operations by software. Because register HxPIN allows reading the pin level also in special output mode, the output state of the specific hardware module may be read by the CPU. Two high current ports together with a coil, build an H-bridge. Two H-bridges are necessary to operate a stepper motor. The n-channel and the p-channel transistor of the output driver are controlled separately, to eliminate crossover currents. The reset output levels of the ports are low to avoid floating coils. See the chapter on pinning for information on specific hardware module connections to individual port pins for special input and special output purposes. H-port control is distributed among five registers. All register bits corresponding to one H-port pin are controlled by the same bus bit. After reset, all H-ports are in normal, output, low, CMOS input level condition. Micronas Feb. 10, 2005; 6251-579-1DS 109 CDC 32xxG-C 14.5. High Current Port Registers Five H-port registers are basically available for 8 H-ports H0 to H7, each. But the respective device's pinning may require a reduction in available H-ports. See the respective pinning table for details. The general H-port register model is given below. P0 to 3 r: Pin Data 0 to 3 Read Pin state. DATA SHEET HxD 7 r/w x x High Current Port x Data Register 6 x x 5 x x 4 x x 3 D3 0 2 D2 0 1 D1 0 0 D0 0 Res D0 to 3 w: r: Data Latch Write latch. Read latch. HxTRI 7 r/w x x High Current Port x Tristate Register 6 x x 5 x x 4 x x 3 T3 0 2 T2 0 1 T1 0 0 T0 0 Res T0 to 3 r/w1: r/w0: Output Tristate Flag 0 to 3 Output driver is disabled (tristate) Output driver is enabled HxNS 7 r/w x x High Current Port x Normal/Special Register 6 x x 5 x x 4 x x 3 S3 0 2 S2 0 1 S1 0 0 S0 0 Res S0 to 3 r/w1: r/w0: Normal/Special Mode Flag 0 to 3 Special Mode. Special hardware drives pin. Normal Mode. Data latch drives pin. HxLVL 7 r/w x x High Current Port x Input Level Register 6 x x 5 x x 4 x x 3 A3 0 2 A2 0 1 A1 0 0 A0 0 Res A0 to 3 r/w1: r/w0: Automotive Flag 0 to 3 Schmitt trigger input level is Automotive Schmitt trigger input level is CMOS HxPIN 7 r x x High Current Port x Pin Register 6 x x 5 x x 4 x x 3 P3 0 2 P2 0 1 P1 0 0 P0 0 Res 110 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 15. AVDD Analog Section The analog section operates from the AVDD supply pin and comprises the PLL/ERM module, the ADC, the P06 and the WAIT comparators. In addition, it contains support circuits like the VREFINT generator, the BVDD regulator and the necessary biasing circuits. Fig. 15-1 gives an overview. External Internal components components 2.5 V 2% ON_5 & en VREFINT Generator VREFINT 2k AVDD AVSS bvdd_err ANAA.BVE +12V WAIT + BVDD Regulator err en 2.5 V BVDD + & en WAIT Comp. ANAA.WAIT WAIT COMP Interrupt Source WAITH fIO ANAA.EP06 & P06 SR0.ADC en R + P06 COMP Interrupt Source R ANAA.P06 P06 Comp. RESETQ SR1.CPUM = 1, 3, 7 PLLC.PMF > 0 en pll_lock lck PLL/ERM 1 1 en ADC VREF, VREF0, VREF1 Fig. 15-1: AVDD section Table 15-1: Activation of AVDD analog section modules Operation Mode RESET FAST, PLL and PLL2 SLOW and DEEP SLOW WAKE, STANDBY, IDLE VREFINT Gen. on on on if PLLC.PMF > 0 or SR0.ADC=1 off off off PLL/ERM and BVDD Regulator off on if PLLC.PMF > 0 ADC, P06, WAIT off on if SR0.ADC=1 Micronas Feb. 10, 2005; 6251-579-1DS 111 CDC 32xxG-C 15.1. VREFINT Generator The VREFINT generator generates bias signals which are necessary for the operation of all analog-section modules. Furthermore, it produces a tightly controlled reference voltage VREFINT, that is delivered to the BVDD regulator and the WAIT comparator. Via a decoupling resistor it is also routed to the VREFINT pin. DATA SHEET The VREFINT pin voltage, which has to be buffered externally by a 10 nF ceramic capacitor, is input to the ADC as alternative, internally generated, reference voltage. This module is permanently enabled during reset, in the CPU modes FAST, PLL and PLL2, and whenever SR0.ADC or PLLC.PMF is not 0. A certain set-up time has to elapse after enabling the module for VREFINT to stabilize. No resistive load must be connected to the VREFINT pin. 15.2. BVDD Regulator The BVDD Regulator generates the 2.5 V BVDD supply voltage for the internal PLL/ERM module from the 5 V AVDD. It derives its reference from the VREFINT generator. BVDD must be buffered externally by a 150 nF ceramic capacitor. This module is permanently enabled whenever PLLC.PMF is not 0. A certain set-up time has to elapse after enable for BVDD to stabilize. An overload condition in the regulator (current or voltage drop-out) is stored in flag ANAA.BVE. The immediate overload signal may be routed to the LCK special output by selection in field ANAU.LS (UVDD analog section). 15.3. Wait Comparator The level on pin WAIT is compared to the internal reference VREFINT. The state of the comparator output is available as flag ANAA.WAIT and as WAIT comparator interrupt source. Furthermore, the output is available on pin WAITH, so that the hysteresis of this comparator can be set with an external positive-feedback resistor (100 kOhms min.). After reset, the module is off (zero standby current). The module is enabled by setting flag SR0.ADC, together with the P0.6 Comparator and the ADC. If the VREFINT generator is powered up as well (cf. Table 15-1), the user has to assure that the necessary VREFINT set-up time has elapsed, before using comparator results (flag and interrupt). The interrupt source output is routed to the interrupt controller logic. But this does not necessarily select it as input to the interrupt controller. Check section "Interrupt Controller" for the actually selectable sources and how to select them. The WAIT comparator interrupt source toggles with fIO, to generate interrupts as long as the level on pin WAIT is lower than the internal reference. 15.4. P0.6 Comparator The level on port P0.6 is compared to AVDD/2. The comparator features a small built-in hysteresis. The state of the comparator output is available as flag ANAA.P06 and as P0.6 Comparator interrupt source. After reset, the module is off (zero standby current). The module is enabled by setting flag SR0.ADC, together with the WAIT comparator and the ADC. If the VREFINT generator is powered up as well (cf. Table 15-1), the user has to assure that the necessary VREFINT set-up time has elapsed, before using comparator results (flag and interrupt). The interrupt source output, which must be enabled by setting flag ANAA.EP06, is routed to the interrupt controller logic. But this does not necessarily select it as input to the interrupt controller. Check section "Interrupt Controller" for the actually selectable sources and how to select them. The P0.6 comparator interrupt source toggles with fIO, to generate interrupts as long as the level on pin P0.6 is lower than the internal reference. 112 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 15.5. PLL/ERM The PLL and ERM modules are operated on the internally generated 2.5 V BVDD supply voltage. For details on operating this module please refer to section "CPU and Clock System". 15.6. A/D Converter (ADC) The analog-to-digital converter allows the conversion of an analog voltage ranging from AVSS to either one of three external references VREF, VREF0, VREF1 (2.5 to 5 V) or the internal reference VREFINT (2.5 V), to a 10-bit digital value. A multiplexer connects one of 16 analog input ports to the ADC. A sample and hold circuit holds the analog voltage during conversion. The duration of the sampling time is programmable. Features - 10-bit resolution. - Successive approximation, charge balance type. - 16-channel input multiplexer. - Input buffering for high ohmic sources selectable. - Sample and hold circuit. - 4/8/16/32 s conversion selectable for optimum throughput/accuracy balance. - 2.5 V internal reference (VREFINT) or 2.5 to 5 V external references (VREF, VREF0, VREF1) selectable - Zero standby current 2 AD0.REF VREF VREFINT VREF0 VREF1 AVDD P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 AVSS 4 MUX AD1.BUF Buf MUX 1 0 S&H A D 10 ADx.AN0 to AN9 Bypass AD0.EOC 2 AD0.TSAMP SR0.ADC ADC-Block en AD0.CHANNEL Fig. 15-2: ADC block diagram 15.6.1. Principle of Operation After reset, the module is off (zero standby current). The module is enabled by setting flag SR0.ADC. The user has to assure that the necessary VREFINT-set-up time has elapsed. Before starting a conversion, select input-buffer usage or bypass with flag AD1.BUF. Note that the input buffer requires Micronas Feb. 10, 2005; 6251-579-1DS 113 CDC 32xxG-C a 1 s setup time before usage. When the buffer is never used, leave flag AD1.BUF cleared. When the buffer is always used, leave this flag set. When toggling buffer usage, set this flag at least 1 s before starting a conversion. Before starting a conversion, check flag AD0.EOC to be set. A conversion is started by a write access to register AD0, selecting sample time (AD0.TSAM), reference source (AD0.REF) and input channel (AD0.CHANNEL). Sampling starts one f0 clock cycle after completion of the write access to AD0. Flag AD0.EOC signals the end of conversion. The 10-bit result is stored in the registers AD1 (8 MSB) and AD0. The conversion time depends on f0 and the programmed sample time (Table 15-2). For the effect of CPU clock modes on the operation of this module refer to section "CPU and Clock System" (see Table 4-1 on page 41). 15.6.1.1. Conversion Law The result of A/D conversion is described by the following formula: DATA SHEET has to make sure that at the end of this sampling period, the voltage on the sampling capacitance is within 0.1 LSB from the source voltage. Measurement errors may occur, when the voltage of highimpedance sources has to be measured: - To reduce these errors, the sampling time may be increased by programming the field AD0.TSAMP. - In cases where high-impedance sources are only rarely sampled, a 100 nF capacitor from the input to AVSS is a sufficient measure to ensure that the voltage on the sampling capacitance reaches the full source voltage, even with the shortest sampling time. - In some high-impedance applications a charge-pumping effect may noticeably influence the measurement result: Charge pumping from a high-potential to a low-potential source will occur when such two sources are measured alternatingly. This results in a current that appears as flowing from the high-potential source through the IC into the low-potential source. This current explains from the fact that during the respective sampling period the highpotential source always charges the sampling capacitance, while the low-potential source always discharges it. Usage of the input buffer (AD1.BUF) substantially reduces this effect. U In DV = INT ------------- 1LSB where U Ref 1LSB = ----------1024 DV = Digital Value; INT = Integer part of the result DV 3FF 3FE 3FD 03 02 01 00 1 23 1021 1023 UIn [LSB] Fig. 15-3: Characteristic curve The voltage on the reference-input pins VREF, VREF0 and VREF1 may be set to any level in the range from AVSS to AVDD. However, accuracy is only specified in the range from 2.56 V (1 LSB = 0.25 mV) to 5.12 V (1 LSB = 0.5 mV). 15.6.1.2. Measurement Errors The result of the conversion mirrors the voltage potential of the sampling capacitance (typically 8 pF) at the end of the sampling time. This capacitance has to be charged by the source through the source impedance within the samplingtime period. To avoid measurement errors, system design 114 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 15.7. Registers register AD0. The result is available until a new conversion is started. 2 TEST AD0 7 r w 0 EOC TSAMP 0 ADC Register 0 6 x 5 x REF 0 4 x 3 x 1 AN1 0 AN0 BUF w1: w0: TEST Input Buffer Usage Buffer used Buffer bypassed for factory use only CHANNEL 0 0 0 0 0 Res ANAA AD1 7 r w AN9 x Analog AVDD Register 6 P06 ADC Register 1 6 AN8 x 7 2 AN4 x 5 WAIT 4 x 3 x 2 x 1 x 0 BVE 0 Res 5 AN7 x 4 AN6 x 3 AN5 x 1 AN3 x 0 AN2 BUF 0 Res r/w EP06 0 EP06 r/w1: r/w0: P06 r1: r0: WAIT r1: r0: BVE r1: r0: w1: w0: Enable P06 Comparator Interrupt Source output Enabled. Disabled. P06 Comparator Output P0.6 is lower than AVDD/2. P0.6 is higher than AVDD/2. WAIT Comparator Output WAIT is lower than VREFINT. WAIT is higher than VREFINT. BVDD Regulator Error Flag Out of specification. Normal operation. Reset flag. No action. EOC End of Conversion r1: End of conversion r0: Busy EOC is reset by a write access to the register AD0. EOC must be true before starting the a conversion. EOC is true after enabling the module by setting SR0.ADC. TSAMP Sampling Time TSAMP adjusts the sample conversion times. Table 15-2: TSAMP usage: Sample and conversion time TSAMP 0H 1H 2H 3H REF w0: w1: w2: w3: tSample 20/f0 60/f0 140/f0 300/f0 tConversion 40/f0 80/f0 160/f0 320/f0 Conversion Reference External reference from VREF pin used Internal reference on VREFINT pin used External reference from VREF0 pin used External reference from VREF1 pin used CHANNEL Channel of Input Multiplexer CHANNEL selects from which pin of port P0 or P1 the conversion is done. The MSB of CHANNEL is bit 3. Table 15-3: CHANNEL usage: ADC input selection CHANNEL 0 to 7 8 to 15 Port Pin P0.0 to P0.7 P1.0 to P1.7 AN 9 to 0 Analog Value Bit 9 to 0 The 10-bit data format is positive integer, i.e., 000H for lowest and 3FFH for highest possible input signal. The 8 MSB can be read from register AD1. The two LSB can be read from Micronas Feb. 10, 2005; 6251-579-1DS 115 CDC 32xxG-C DATA SHEET 116 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 16. Timers (TIMER) Five general-purpose timers are implemented. T0 is a 16-bit timer, T1 to T4 are 8-bit timers. 16.1. Timer T0 Timer T0 is a 16-bit auto reload down counter. Its function is to deliver a timing reference signal to the ICU, to output a frequency signal or to produce time stamps. Features - 16-bit auto reload counter - Time value readable - Interrupt source output - Frequency output w HW Option T0C clk Reload-Reg. 16 TIM0 1/2 tclk tclk TIM0 underflow & 1/2 res T0 Interrupt Source T0-OUT r clk 16 bit Auto-reload Down counter Fig. 16-1: Timer T0 block diagram 16.1.1. Principle of Operation 16.1.1.1. General The timer's 16-bit down-counter is clocked by the input clock and counts down to zero. One clock count after reaching zero, it generates an output pulse, reloads with the content of the TIM0 reload register and restarts its travel. For the effect of CPU clock modes on the operation of this module refer to section "CPU and Clock System" (see Table 4-1 on page 41). 16.1.1.2. Operation The clock input frequency is settable by HW option (see Table 16-1 on page 118). Prior to entering active mode, proper SW initialization of the U-ports assigned to function as T0-OUT outputs has to be made (Table 16-1). The ports have to be configured special out. Refer to "Ports" for details. T0 is always active (no standby mode). After reset, the timer starts counting with reload value 0xFFFF generating a maximum period output signal. A new time value is loaded by writing to the 16-bit register TIM0, high byte first. Upon writing the low byte, the reload register is set to the new 16-bit value, the counter is reset, and immediately starts down-counting with the new value. After reaching zero, on wrapping to 0xFFFF, the counter generates a reload signal, which can be used to trigger an interrupt. The same signal is connected to a divide-by-two scaler to generate the output signal T0-OUT with a pulse duty factor of 50%. The interrupt source output of this module is routed to the interrupt controller logic. But this does not necessarily select it as input to the interrupt controller. Check section "Interrupt Controller" for the actually selectable sources and how to select them. The state of the down-counter is readable by reading the 16bit register TIM0, low byte first. Upon reading the low byte, the high byte is saved to a temporary latch, which is then accessed during the subsequent high byte read. Thus, for time stamp applications, read consistency between low and high byte is guaranteed. 16.1.1.3. Precautions Use 8-bit load/store operations to access Timer 0 register rather than 16-bit access. A load with a new value within a time period of < tclk/2 before a scheduled interrupt source output signal, can no longer cancel this signal. It will appear at the interrupt source output anyway (See fig. 16-2 for details). Thus, after loading a new time value, wait at least tclk/2 before resetting the pending flag P and enabling the interrupt channel. Micronas Feb. 10, 2005; 6251-579-1DS 117 CDC 32xxG-C DATA SHEET clk tclk counter 2 1 0 Reload Value Reload Value - 1 underflow critical period for loading interrupt Fig. 16-2: Timer0 timing Table 16-1: Module-specific settings Module Name T0 HW Options Item Input clock Address T0C Initialization Item T0-OUT output Setting U1.2 special out Enable Bit 16.1.2. Registers TIM0L 7 r w 1 T0 low byte 6 5 4 3 2 1 0 Read low byte of down-counter and latch high byte Write low byte of reload value and reload down-counter 1 1 1 1 1 1 1 Res TIM0H 7 r w 1 1 T0 high byte 6 5 4 3 2 1 0 Latched high byte of down-counter High byte of reload value 1 1 1 1 1 1 Res TIM0 has to be read low byte first and written high byte first. Table 16-2: Reload register programming Reload value 0x0000 0x0001 0x0002 : 0xFFFF Output interrupt source frequency is divided by 1 2 3 : 65536 Output T0-OUT is divided by 2 4 6 : 131072 118 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 16.2. Timer T1 to T4 Timer T1 to T4 are 8-bit auto reload down counters. They serve to deliver timing reference signals to the ICU or to output frequency signals. Table 16-3 describes implementation-specific HW option addresses and enable flags of T1 to T4. Features - 8-bit auto reload counter - Interrupt source output - Frequency output w HW Option TxC clk Reload-Reg. 8 tclk TIMx 1/2 tclk Tx Interrupt Source 1/2 res Tx-OUT & enable clk 8 bit Auto-reload Down counter underflow & Fig. 16-3: Timer T1 to T4 block diagram 16.2.1. Principle of Operation 16.2.1.1. General The timer's 8-bit down-counter is clocked by the input clock and counts down to zero. One clock count after reaching zero, it generates an output pulse, reloads with the content of the TIMx reload register and restarts its travel. For the effect of CPU clock modes on the operation of this module refer to section "CPU and Clock System" (see Table 4-1 on page 41). 16.2.1.2. Operation The clock input frequencies can be set with HW options (see Table 16-3 on page 120). After reset, the 8-bit timer is in standby (inactive) mode. Prior to entering active mode, proper SW initialization of the U-Ports assigned to function as Tx-OUT outputs has to be made (Table 16-3). The ports have to be configured as special out. Refer to "Ports" for details. To initialize a timer, reload register TIMx can be set to the desired time value already in standby mode. For entering active mode, set the corresponding enable bit in the standby registers (see Table 16-3 on page 120). The timer will immediately start counting down from the time value present in register TIMx. During active mode, a new time value is loaded by simply writing to register TIMx. Upon writing, the counter is reset, and immediately starts counting down from the new time value. After reaching zero, on wrapping to 0xFF, the counter generates a reload signal, which can be used to trigger an interrupt. The same signal is connected to a divide by two scaler to generate the output signal Tx-OUT with a pulse duty factor of 50%. The interrupt source output of this module may be but must not be connected to the interrupt controller. Please refer to section interrupt controller. Returning Tx to standby mode by resetting its respective enable bit will halt its counter and will set its outputs LOW. The register TIMx remains unchanged. The state of the down-counter is not readable. 16.2.1.3. Precautions A load with a new value within a time period of < tclk / 2 before a scheduled interrupt source output signal, can no longer cancel this signal. It will appear at the interrupt source output anyway (See Fig. 16-4 for details). Furthermore, disabling the timer within a time period of < tclk / 2 before a scheduled interrupt source output signal, will immediately generate an extra interrupt source output signal. Re-enabling the timer afterwards will lead to generation of the previously scheduled interrupt source output signal, because it was stored internally. This latter interrupt source output signal will be generated even if a new time value is loaded during the inactive time. Thus after configuring and (re-)enabling the timer, or after loading a new time value during active mode, wait at least tclk / 2 before resetting the pending flag P and (re-)enabling the interrupt channel. Micronas Feb. 10, 2005; 6251-579-1DS 119 CDC 32xxG-C DATA SHEET clk tclk counter 2 1 0 Reload Value Reload Value - 1 underflow critical period for disabling/enabling and/or loading interrupt Fig. 16-4: Timer1 to 4 timing Table 16-3: Module-specific settings Module Name T1 T2 T3 T4 HW Options Item Input clock Input clock Input clock Input clock Address T1C T2C T3C T4C Initialization Item T1-OUT output T2-OUT output T3-OUT output T4-OUT output Setting U1.1 special out U1.0 special out U0.7 special out U0.6 special out, PM.U06 = 0 SR0.TIM1 SR0.TIM2 SR0.TIM3 SR0.TIM4 Enable Bit 16.2.2. Registers TIMx 7 w 0 0 0 Timer x 6 5 4 3 2 1 0 Reload value 0 0 0 0 0 Res Table 16-4: Reload register programming Reload value 0x00 0x01 0x02 : 0xFF Output interrupt source frequency is divided by 1 2 3 : 256 Output Tn-OUT is divided by 2 4 6 : 512 120 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 17. Pulse Width Modulator (PWM) A PWM is an auto-reload down-counter with fixed reload interval. It serves as a generator of a frequency signal with variable pulse width or, with an external low-pass filter, as a digital-to-analog converter. This module is combined of two independently operable 8-bit PWMs which can be combined to a single 16-bit PWM. The number of PWMs implemented is given in table 17-1. The "x" in register names distinguishes the module number and can be 1, 3, 5, 7, 9, 11. Features - Two 8-bit or one 16-bit pulse width modulator - Wide range of HW-option-selectable cycle frequencies LSB period clock 1 PWMx-1 8 MSB PWMx 8 PxP PxC SQ R 1 PWMx-1 0 HW Option clk load en ovf 8-bit down counter 0 clk load 1 1 0 en ovf 8-bit down counter SQ R 1 0 PWMx SR1.PWMx PWMC.P16x 1 x = 1, 3, 5, 7, 9, 11 Fig. 17-1: PWM block diagram 17.1. Principle of Operation 17.1.1. General A PWM's down-counter is clocked by its input clock and counts down to zero. Reaching zero, it stops and sets the output to LOW. A period input pulse reloads the counter with the content of the PWM register, restarts it and sets the output to HIGH. For the effect of CPU clock modes on the operation of this module refer to section "CPU and Clock System" (see Table 4-1 on page 41). 17.1.3. Initialization Prior to entering active mode, proper SW initialization of the H-Ports and U-Ports assigned to function as PWMx outputs has to be made (Table 17-1). The ports have to be configured special out. Refer to "Ports" for details. It has to be decided which PWM module shall work as one 16-bit or as two 8-bit PWMs. Selection has to be done via the PWM control register PWMC as long as the PWM module is disabled. 17.1.2. Hardware settings The clock and period input frequencies can be set by HW option (Table 17-1). There is one common source for both 8bit PWMs, one for clock and one for period, thus clock and period are not independently selectable for the two 8-bit PWMs. For full resolution, a clock-to-period frequency ratio of 256 (65536 in 16-bit mode) is recommended. Should other ratios be used, make sure that the combination of clock, period and pulse width setting allow the PWM to generate an output signal with a LOW transition. Some of the PWM outputs share pins with outputs of other modules. The output multiplexer is controlled by HW option (Table 17-1). 17.1.4. Operation After reset, a PWM is in standby mode (inactive) and the output signal PWMx is LOW. For entering active mode, select the desired mode (8-/16-bit mode) and then set the respective enable bit (Table 17-1). Then write the desired pulse width value to register PWMx (write low byte first in 16-bit mode). Each PWM will start producing its output signal immediately after the next subsequent input pulse on its period input. During active mode, a new pulse width value is set by simply writing to the register PWMx. Upon the next subsequent input pulse on its period input the PWM will start producing an output signal with the new pulse width value, starting with a HIGH level. Micronas Feb. 10, 2005; 6251-579-1DS 121 CDC 32xxG-C Table 17-1: Module-specific settings Module Name PWM1 HW Options Item Clock and period H0.3 SMG/PWM1 output multiplexer PWM3 Clock and period H0.2 SMG/PWM3 output multiplexer PWM5 Clock and period H7.3 SME/PWM4 output multiplexer H0.1 SMG/PWM5 output multiplexer PWM7 Clock and period H7.2 SME/PWM6 output multiplexer H0.0 SMG/PWM7 output multiplexer PWM9 Clock and period H7.1 SME/PWM8 output multiplexer H7.0 SME/PWM9 output multiplexer PWM11 Clock and period Address P1C, P1P PM.H0 P3C, P3P PM.H0 P5C, P5P PM.H7 PM.H0 P7C, P7P PM.H7 PM.H0 P9C, P9P PM.H7 PM.H7 P11C, P11P PWM8 PWM9 PWM10 PWM11 Returning a PWM to standby mode by resetting its respective enable flag will immediately set its output LOW. The 8-bit PWM output PWMx-1 is not usable in 16-bit mode. The state of the down-counters and the PWM registers is not readable. H7.1 and/or H6.3 special out H7.0 and/or H6.2 special out H6.1 special out H6.0 special out PWM6 PWM7 H7.2 special out H0.0 special out PWM4 PWM5 H7.3 special out H0.1 special out Initialization Item PWM0 PWM1 PWM2 PWM3 Setting U0.3 special out U0.2 and/or H0.3 special out U0.1special out U0.0 and/or H0.2 special out DATA SHEET Enable Bit SR1.PWM1 SR1.PWM3 SR1.PWM5 SR1.PWM7 SR1.PWM9 SR1.PWM11 Due to EMI reduction the start of a period is delayed for different PWMs (Table 17-2). Table 17-2: Module delay Module Number PWM 0, 4, 8 PWM 1, 5, 9 PWM 2, 6, 10 PWM 3, 7, 11 Delay 0 1/f0 2/f0 3/f0 17.2. Registers PWMx 7 w 0 0 PWMx Register 6 5 4 3 2 1 0 PWMx-1 7 w 0 0 0 Res 0 0 PWMx-1 Register 6 5 4 3 2 1 0 Pulse width value 0 0 0 Pulse width value 0 0 0 0 0 0 Res 122 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Table 17-3: 8-bit mode pulse width programming Pulse width value 0x00 0x01 0x02 : 0xFE 0xFF 1) Pulse duty factor 0% (Output is permanently low) 1/256 2/256 : 254/256 100% (Output is permanently high) 1) Pulse duty factor 255/256 is not selectable. Table 17-4: 16-bit mode pulse width programming Pulse width value 0x0000 0x0001 0x0002 : 0xFFFE 0xFFFF 1) Pulse duty factor 0% (Output is permanently low) 1/65536 2/65536 : 65534/65536 100% (Output is permanently high) 1) Pulse duty factor 65535/65536 is not selectable. PWMC 7 w x x PWM Control Register 6 x x 5 P1611 0 4 P169 0 3 P167 0 2 P165 0 1 P163 0 0 P161 0 Res P16x w1: w0: PWM 16 Mode of Module x 16-bit mode. 8-bit mode. Micronas Feb. 10, 2005; 6251-579-1DS 123 CDC 32xxG-C DATA SHEET 124 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 18. Pulse Frequency Modulator (PFM) The PFM generates a signal with variable frequency and variable pulse width. Together with external elements, it may serve to generate a negative voltage for LCD elements. Features - Pulse width and period separately controllable - Pulse width and period counters operate with HW option selectable clock - Output polarity selectable - Standby mode 8-bit Reload-reg. HW Option PF0C 1 0 Pulse Width PFMx.INV 0 1 0 clk ld en 8-bit Down Counter zero 1 1 1 PFMx ld clk 16-bit Down Counter zero 16-bit Reload-reg. SR1.PFMx Period Length Fig. 18-1: PFM block diagram 18.1. Principle of Operation 18.1.1. General The pulse width and the period counter start synchronously with down-counting. As long as the pulse width counter is running, its zero output is LOW. When this counter reaches zero, it stops counting and sets the zero output to HIGH. When the period counter reaches zero, it reloads both counters, which starts a new count cycle. The zero output of the pulse width counter can be driven out directly or inverted via pin PFMx. The module is operable in PLL, FAST and SLOW mode. As long as PF0C is available it is also operable in DEEP SLOW mode. See also chapter "CPU and Clock System" for further details. Table 18-1: Module-specific settings HW Options Item Input clock Address PF0C Initialization Item PFM0 Setting U5.0 and/or U1.7 special out U7.5 special out 1) SR1.PFM0 Enable Bit 18.1.2. Hardware Settings The clock input frequency PF0C can be set by HW option (see Table 18-1). Input clock PF0C PFM1 SR1.PFM1 1) Make sure that flag LE in register ANAU is set to zero, otherwise an internal test signal is output at this pin. 18.1.3. Initialization Prior to entering active mode, proper SW initialization of the U-Ports assigned to function as PFMx output has to be made (Table 18-1). The ports have to be configured as special out. Refer to "Ports" for details. Micronas Feb. 10, 2005; 6251-579-1DS 125 CDC 32xxG-C 18.1.4. Operation After reset the PFM is in standby mode (inactive) and the output signal is LOW. To prepare for active mode, write new values, if needed, for the pulse width and the period length to the respective PFMx register and select output inversion, if necessary, with flag INV. For entering active mode set the enable bit SR1.PFMx. Changing the PFMx register setting during active mode, is simply done by writing a 32-bit word to this register. After the register has been updated, the PFM will produce an output DATA SHEET signal with the new pulse width and period length starting with the next subsequent load signal of the period counter. For data consistency, when using 8-bit and 16-bit writes, new values will only become valid after a write to the pulsewidth register (byte 2 in the PFMx register). Returning the PFM to standby mode by clearing its enable bit SR1.PFMx will immediately set its output to INV and disable the clock input. The content of the PFMx register is not affected by standby mode. The state of the counters and the reload registers is not readable. 18.2. Registers Table 18-2 shows the relation between the pulse width and the period length and its effect on the PFMx output. Offs 3 2 PFMx 7 w w w w INV Pulse Width and Period Register 6 x 5 x 4 x 3 x 2 x 1 x 0 x Table 18-2: Pulse width to period length relation Pulse Width 0 Period Length x Pulse Width > Pulse Width x Pulse Width > Pulse Width 1 INV 0 PFMx output Always low Always high High pulses Always high Always low Low pulses Pulse Width Period Length (High Byte) Period Length (Low Byte) 0x00 1 0 Res >0 >0 0 >0 >0 INV r/w1: r/w0: Invert Output Signal inverted direct The pulse width counter zero output HIGH time is calculated by t HIGH = Pulse Width ---------------------------F PF0C and the duration of the period time by t Period = Period Length --------------------------------F PF0C Therefore, the pulse width counter zero output LOW time is t LOW = t Period - t HIGH 126 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 19. Capture Compare Module (CAPCOM) The IC contains two capture compare modules (CAPCOM). A CAPCOM is a complex relative timer. It comprises a freerunning 16-bit capture compare counter (CCC) and a number of subunits (SU). The timer value can be read by SW. A SU is able to capture the relative time of an external event input and to generate an output signal when the CCC passes a predefined timer value. Three types of interrupts enable interaction with SW. Special functionality provides an interface to the asynchronous external world. - 16-bit free-running counter with read-out. - 16-bit capture register. - 16-bit compare register. - Input trigger on rising, falling or both edges. - Output action: toggle, low or high level. - Three different interrupt sources: overflow, input, compare - Designed for interface to asynchronous external events HW Option fC1C SR0.CCC1 fCC1IN clk CCC1 Timer Value 16 ofl CCC1OFL Interrupt Source 2 2 1 fIO clock CC4I 1 0 CAP CMP OFL LAC RCR X X X CC4M MCAP MCMP MOFL FOL OAM IAM CC4-IN 00 01 10 11 Input Action Logic 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 & CC4OR Interrupt Source & >1 3 2 & 1 fIO clock CC4-OUT LOW 0 0 TOGGLE 0 1 10 11 Output Action Logic >1 16 reset load A B = 16-bit Capture Register 16-bit Compare Register r w 16 CC4COMP Interrupt Source Subunit 4 CC4 Timer Value 16 1 fIO clock ofl CC5-IN CC5-OUT CC5OR Subunit 5 CC5COMP Fig. 19-1: CAPCOM module 1 block diagram Micronas Feb. 10, 2005; 6251-579-1DS 127 CDC 32xxG-C DATA SHEET HW Option fC0C SR0.CCC0 fCC0IN clk CCC0 Timer Value 16 ofl CCC0OFL Interrupt Source 2 2 1 fIO clock CC0I 1 0 CAP CMP OFL LAC RCR X X X CC0M MCAP MCMP MOFL FOL OAM IAM CC0-IN 00 01 10 11 Input Action Logic 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 & CC0OR Interrupt Source & >1 3 2 & 1 fIO clock CC0-OUT LOW 0 0 TOGGLE 0 1 10 11 Output Action Logic >1 16 reset load A B = 16-bit Capture Register 16-bit Compare Register r w 16 CC0COMP Interrupt Source Subunit 0 CC0 Timer Value 16 1 fIO clock ofl CC1-IN CC1-OUT CC1OR Subunit 1 Timer Value 16 CC1COMP ofl CC2-IN CC2-OUT CC2OR Subunit 2 Timer Value 16 CC2COMP ofl CC3-IN CC3-OUT CC3OR Subunit 3 CC3COMP Fig. 19-2: CAPCOM module 0 block diagram 128 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 19.1. Principle of Operation 19.1.1. General The capture compare module (CAPCOM, Fig. 19-1, 19-2) contains one common free-running 16-bit counter (CCC) and a number of capture and compare subunits (SU). More details are given in Tables 19-1 and 19-2. The timer value can be read by SW from 16-bit register CCC. The CCC provides an interrupt on overflow. Each SU is able to capture the CCC value at a point of time given by an external input event processed by an input action logic. A SU can also change an output line level via an output action logic at a point of time given by the CCC value. Thus, a SU contains a 16-bit capture register CCx to store the input event CCC value, a 16-bit compare register CCx to program the output action CCC value, an 8-bit interrupt register CCxI and an 8-bit mode register CCxM. Two types of interrupts per SU enable interaction with SW. The interrupt source output of this module is routed to the interrupt controller logic. But this does not necessarily select it as input to the interrupt controller. Check section "Interrupt Controller" for the actually selectable sources and how to select them. For the effect of CPU clock modes on the operation of this module refer to section "CPU and Clock System" (see Table 4-1 on page 41). SU3 Please note that the compare register CCx is reset in standby mode. It can only be programmed in active mode. Table 19-1: Unit 0 specific settings Subunit SU0 Input SU1 Input SU2 Input PM. CACO PM. CACO PM. CACO HW Options Item Initialization Setting U3.2, U4.0 special out U3.2, U4.1 special in U3.1, U2.5 special out U3.1, U2.4 special in U3.0, U2.3 special out U3.0, U2.2 special in U0.5, U0.6, U8.1 special out U0.6 special in SR0. CCC0 Enable Bit Address Item CC0OUT CC0-IN CC1OUT CC1-IN CC2OUT CC2-IN CC3OUT CC3-IN 19.1.2. Hardware Settings The CCC0 and CCC1 clock frequency must be set via HW option (Table 19-1 and 19-2). Some SUs use several ports. They can be selected via HW option port multiplexer (PM). Refer to "HW Options" for setting them. Output PM. U06 19.1.3. Initialization After system reset the CCC and all SUs are in standby mode (inactive). In standby mode, the CCC is reset to value 0x0000. Capture and compare registers CCx are reset (comp. reg to 0xFFFF, capt. reg to 0x0). No information processing will take place, e.g., update of interrupt flags. However, the values of registers CCxI and CCxM are only reset by system reset, not by standby mode. Thus it is possible to program all mode bits in standby mode and a predetermined start-up out of standby mode is guaranteed. The flags CCxI.CAP, CCxI.CMP and CCxI.OFL are read-only during standby mode. Prior to entering active mode, proper SW configuration of the U-Ports, assigned to function as input capture inputs and output action outputs has to be made (Table 19-1, 19-2). The output action ports have to be configured as special out and the Input Capture ports as special in. Refer to "Ports" for details. 19.1.3.1. Subunit For a proper setup the SW has to program the following SU control bits in registers CCxI and CCxM: interrupt mask (MSK), force output logic (FOL, 0 recommended), output action mode (OAM), input action mode (IAM), reset capture register (RCR, 0 recommended), and lock after capture (LAC). Refer to section 19.2. for details. SU0, SU1, SU2, SU3 Clock C0C Table 19-2: Unit 1 specific settings Subunit SU4 Input SU5 PM. CC4I HW Options Item Initialization Setting U5.3, U8.0 special out U5.3, P0.0 special in U7.4 special out U7.4 special in SR0. CCC1 Enable Bit Address Item CC4OUT CC4-IN CC5OUT CC5-IN SU4, SU5 Clock C1C Micronas Feb. 10, 2005; 6251-579-1DS 129 CDC 32xxG-C 19.1.4. Operation of CCC For entering active mode of the entire CAPCOM module set the enable bit (Table 19-1 and 19-2). The CCC will immediately start up-counting with the selected clock frequency and will deliver this 16-bit value to the SUs. The state of the counter is readable by reading the 16-bit register CCC, low byte first. Upon reading the low byte, the high byte is saved to a temporary latch, which is then accessed during the subsequent high byte read. Thus, for time stamp applications, read consistency between low and high byte is guaranteed. The CCC is free-running and will overflow from time to time. This will cause the generation of an overflow interrupt event. The interrupt (CCCxOFL) is directly fed to the interrupt controller and also to all SUs where further processing takes place. DATA SHEET ations the lock after capture (LAC) mode is implemented. If bit CCxI.LAC is set, only one capture event will pass. After this event has triggered a capture, the input action logic will lock until it is unlocked again by writing an arbitrary value to register CCxM. Make sure that this write only restores the desired setting of this register. Programming the input action logic while an input transition occurs may result in an unexpected triggering. This may overwrite the capture register, lock the input action logic if in LAC mode and generate an interrupt. Make sure that SW is prepared to handle such a situation. For testing purposes, a permanent reset (0xFFFF) may be forced on capture register CCx by setting bit CCxI.RCR. Make sure that the reset is only temporary. 19.1.5.3. Interrupts Each SU supplies two internal interrupt events: 1. Input capture event and 2. Comparator equal state. 19.1.5. Operation of Subunit 19.1.5.1. Compare and Output Action To activate a SUs compare logic the respective 16-bit compare register CCx has to be programmed, low byte first. The compare action will be locked until the high byte write is completed. As soon as CCx setting and CCC value match, the following actions are triggered: - The flag CMP in the CCxI register is set. - The CCxCOMP interrupt source is triggered. - The CCxOR interrupt source is triggered if activated. - The output action logic is triggered. Four different reactions are selectable for the output action signal: according to field CCxM.OAM (Table 19-3) the equal state will lead to a high or low level, toggling or inactivity on this output. Another way to control the output action is bit CCxM.FOL. For instance, rise-mode and force will set the output pin to high level, fall-mode and force to low level. This forcing is static, i.e., it will be permanently active and may override compare events. Thus it is recommended to set and reset shortly after that, i.e., to pulse the bit with SW. Toggle mode of the output action logic and forcing leads to a burst with clock-frequency and is not recommended. 19.1.5.2. Capture and Input Action The input action logic operates independently of the output action logic and is triggered by an external input in a way defined by field CCxM.IAM. Following Table 19-4 it can completely ignore events, trigger on rising or falling edge or on both edges. When triggered, the following actions take place: - Flag CCxI.CAP is set. - The CCxOR interrupt source is triggered if activated. - The 16-bit capture register CCx stores the current CCC value, i.e., the "time" of the external event. Read CCx low byte first. Further capture and input action will be locked until the subsequent high byte read is completed. Thus a coherent result is ensured, no matter how much time has elapsed between the two reads. Some applications suffer from fast input bursts and a lot of capture events and interrupts in consequence. If the SW cannot handle such a rate of interrupts, this could evoke stack overflow and system crash. To prevent such fatal situ- In addition to the above-mentioned two interrupt events, the CCC overflow interrupt event sets flag CCxI.OFL in each SU. Thus, three interrupt events are available in each SU. As previously explained, interrupt events will set the corresponding flags in register CCxI. Those three interrupt events are masked with their mask bits in register CCxM and passed to a logical or. The result (CCxOR) is fed to the interrupt controller as a first interrupt source. In addition, the comparator equal (CCxCOMP) interrupt is directly passed to the interrupt controller as second interrupt source. Thus a SU offers four types of interrupts: CCC overflow (maskable ored), input capture event (maskable ored) and comparator equal state (maskable ored and non-maskable direct). All interrupt sources act independently, parallel interrupts are possible. The interrupt flags enable SW to determine the interrupt source and to take the appropriate action. Before returning from the interrupt routine the corresponding interrupt flag should thus be cleared by writing a 1 to the corresponding bit location in register CCxI. The interrupts generated by internal logic (CCC overflow and comparator equal) will trigger in a predetermined and known way. But as explained in 19.1.5.2. erroneous input signals may cause some difficulties concerning the input capture input as well as interrupt handling. To overcome possible problems the input capture Interrupt flag CCxI.CAP is double-buffered. If a second or even more input capture interrupt events occur before the interrupt flag is cleared (i.e. SW was not able to keep track), the flag goes to a third state. Two consecutive writes to this bit in register CCxI are then necessary to clear the flag. This enables SW to detect such a multiple interrupt situation and eventually to discard the capture register value, which always relates to the latest input capture event and interrupt. The internal CAPCOM module control logic always runs on the clock divider chain f0 frequency, regardless of CPU clock mode. Avoid write accesses to the CCxI register in CPU slow mode since the logic would interpret one CPU access as many consecutive accesses. This may yield to unexpected results concerning the functionality of the interrupt flags. The following procedure should be followed to handle the capture interrupt flag CAP: 1. SW responds to a CAPCOM interrupt, switching to CPU Fast or PLL mode if necessary and determining that the 130 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 19.1.6. Inactivation The CAPCOM module is inactivated and returned to standby mode (power down mode) by setting the enable bit to 0. Section 19.1.3. applies. CCxI and CCxM are only reset by system reset, not by standby mode. source is a capture interrupt (CAP flag =1). 2. The interrupt service routine is processed. 3. Just before returning to main program, the service routine acknowledges the interrupt by writing a 1 to flag CAP. 4. The service routine reads CAP again. If it is reset, the routine can return to main program as usual. If it is still set, an external capture event overrun has happened. Appropriate actions may be taken (i.e., discarding the capture register value etc.). 5. go to 3. 19.1.7. Precautions The CCxI register must not be written in CPU Slow mode (see Section 19.1.5.3. on page 130). Read-Modify-Write operations on single flags of register CCxI must be avoided. Unwanted clearing of other flags of this register may be the result otherwise. 19.2. Registers The CAPCOM counter and the Capture/Compare registers have to be read/written low byte first to avoid inconsistencies. The memory controller accesses multiple byte quantities low byte first. Thus the 16-bit CAPCOM counter and the 16-bit capture/compare registers can be accessed 16 bit wide. can trigger, nor SW can force the output action logic by writing another "one". After forcing it is recommended to clear FOL unless output action logic should not be locked. OAM r/w: Output Action Mode Defines behavior of Output Action logic. Table 19-3: OAM usage CCCyL 7 r 0 0 CAPCOM Counter low byte 6 5 4 3 2 1 0 Bit 32 00 Res Output Action Logic Modes Disabled, ignore trigger, output low level. Toggle output. Output low level. Output high level. Input Action Mode Defines behavior of Input Action logic. Read low byte and lock CCC 0 0 0 0 0 0 01 CCCyH 7 r 0 0 CAPCOM Counter high byte 6 5 4 3 2 1 0 10 11 IAM r/w: Read high byte and unlock CCC 0 0 0 0 0 0 Res Table 19-4: IAM usage CCxM 7 r/w MCAP 0 CAPCOM x Mode Register 6 MCMP 0 5 MOFL 0 4 FOL 0 3 OAM 0 2 1 IAM 0 Bit 10 00 Res Input Action Logic Modes Disabled, don't trigger. Trigger on rising edge. Trigger on falling edge. Trigger on rising and falling edge. 0 0 0 01 MCAP r/w1: r/w0: MCMP r/w1: r/w0: MOFL r/w1: r/w0: Mask CAP Flag Enable. Disable. Mask CMP Flag Enable. Disable. Mask OFL Flag Enable. Disable. 10 11 CCxI 7 r/w CAP 0 CAPCOM x Interrupt Register 6 CMP 0 5 OFL 0 4 LAC 0 3 RCR 0 2 x 0 1 x 0 0 x 0 Res FOL Force Output Action Logic r/w1: Force Output Action logic. r/w0: Release Output Action logic. This flag is static. As long as FOL is true, neither comparator Micronas Feb. 10, 2005; 6251-579-1DS 131 CDC 32xxG-C CAP r1: r0: w1: w0: CMP r1: r0: w1: w0: OFL r1: r0: w1: w0: Capture Event Event. No Event. Clear flag. No change. Compare Event Event. No Event. Clear flag. No change. Overflow Event Event. No Event. Clear flag. No change. DATA SHEET LAC Lock After Capture r/w1: Enable. r/w0: Disable. Refer to section 19.1.5.2. RCR r/w1: r/w0: Reset Capture Register Reset capture register permanently to 0xFFFF. Release capture register. CCxL 7 r w 1 CAPCOM x Capture/Compare Register low byte 6 5 4 3 2 1 0 Read low byte of capture register and lock it. Write low byte of compare register and lock it. 1 1 1 1 1 1 1 Res CCxH 7 r w 1 CAPCOM x Capture/Compare Register high byte 6 5 4 3 2 1 0 Read high byte of capture register and unlock it. Write high byte of compare register and unlock it. 1 1 1 1 1 1 1 Res 132 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 20. Stepper Motor Module (SMM) The SMM serves as a controller for air-cored movements or stepper motors that are directly coupled in H-bridge formation to H-Ports. Upon CPU programming it creates all waveforms necessary to position the drive pointer as desired. The number of motors that are controllable by subunits (control units) of the module is given in Table 20-4. Features - Multichannel pulse-width modulated output - Outputs offset for improved EMC properties - Four quadrant operation - 8-bit resolution - HW option selectable output cycle frequency 20.1. Functional Description 20.1.1. General An 8-bit, free-running counter FRC (Fig. 20-2) operates on the fSM input clock (generally 4 MHz) and creates an 8-bit counter word that is fed to a number of control units SMx. A control unit (Fig. 20-2) contains 8-bit sine and cosine compare registers. One comparator each is associated with these registers and creates a compare signal when register content and FRC word are equal. An output flip-flop associated with each comparator is set when the FRC word is zero and reset by the respective compare signal. A delay stage associated with each control unit delays the flip-flop output signals by a fixed number of fSM cycles to achieve non-synchronism between the output signals of the various control units, thus achieving an improved EMC behavior of the SMV (cf. Fig. 20-1). According to the setting of a quadrant register associated with each control unit, each of a unit's two output signals is multiplexed to signals SMxn+ and SMxn- so as to properly control 2 individual H-Ports that form an H-bridge together with the connected motor coil. By these means, a control unit supplies two H-bridges with signals SMx1+, SMx1-, SMx2+ and SMx2- to function as variable pulse width modulator outputs with selectable polarity. Summing up: when the compare registers are set to the sine and cosine value of a desired rotor angle and the quadrant register is set to the desired quadrant, an air cored movement or a stepper motor connected to the unit's 4 H-Ports will carry the proper average coil currents of proper polarity so that its rotor will assume the desired rotary angle. Three registers control readjustment of a rotor to a new angle. Sine, cosine and unit/quadrant registers serve as temporary storage of new sine, cosine, related quadrant and unit selection values. A scheduler logic times the synchronous downloading of the three buffered words to the respective unit's sine, cosine and quadrant registers, so as to avoid inconsistencies among them. A busy bit may be read out, signaling completion of the downloading. 1/ftrig ftrig =fSM /28 SMA1+ SMA1- SMA2+ tdA = 0/ fSM SMA2- SMB1+ SMB1- SMB2+ tdB = 1/ fSM SMB2- Fig. 20-1: Timing diagram of output signals Example: SMB in 4th quadrant Example: SMA in 1st quadrant Micronas Feb. 10, 2005; 6251-579-1DS 133 CDC 32xxG-C DATA SHEET SMVC SR0.SM fSM fSM /256 w xx SEL 3 x QUAD Busy Load ftrig fCLK 7 OVFL Scheduler 8-bit FRC SMVSIN r xxxxxxxB Sine register w Comparator sin A "=" sin A comp. latch (reload register) RS DELAY Q 0/f SM sin Quadrant register and decoder SMA1+ SMA1SMA2+ SMA2- Load A Comparator cos A "=" cos A comp. latch (reload register) RS DELAY Q 0/f SM cos SMA SMB1+ SMB1DELAY 1 / fSM SMVCOS Cosine register sin B / cos B SMB2+ SMB SMB2- SMC1+ w SMC1sin C / cos C DELAY 2 / fSM SMC2+ SMC SMC2- SMD1+ SMD1sin D / cos D DELAY 3 / fSM SMD2+ SMD HW Option PWM4 PWM6 sin E / cos E DELAY 4 / fSM SMD2- SME1+ SME1SME2+ SME2- SME PWM8 PWM9 SMF1+ SMF1sin F / cos F DELAY 5 / fSM SMF2+ SMF HW Option SMF2- SMG1+ PWM1 SMG1sin G / cos G DELAY 6 / fSM PWM3 SMG2+ PWM5 SMG2PWM7 SMG Fig. 20-2: Block diagram of output generation circuit 134 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 20.2. Registers SMVC 7 w x x SMM Control Register 6 x x 0 SMVSIN 1 QUAD 0 0 Res SMM Sine Register 6 x 5 4 SEL 0 3 2 x 0 r w 7 x 5 x 4 x 3 x 2 x 1 x 0 BUSY 0 x 8bit Sine Value 0 0 0 0 0 0 0 0 Res SEL QUAD Control unit Selection field (Table 20-1) Quadrant selection field (Table 20-2) Table 20-1: SEL usage SEL 000 001 010 011 100 101 110 111 selected control unit SMA SMB SMC SMD SME SMF SMG Not permitted SMVCOS 7 w 0 0 SMM Cosine Register 6 5 4 3 2 1 0 8bit Cosine Value 0 0 0 0 0 0 Res BUSY r0: r1: Scheduler Busy Flag Scheduler not busy Scheduler busy, do not write registers SMVC, SMVCOS, SMVSIN Table 20-3: Usage of SMVSIN and SMVCOS registers Value 0x00 0x01 0x02 Duty factor 0/256 (continuously low) 1/256 2/256 : 254/256 255/256 1) Pulse Diagram Table 20-2: QUAD setting and resulting control unit output signal function QUAD Control unit output signal function SMx1+ 00 01 10 11 sine sine VSS VSS SMx1VSS VSS sine sine SMx2+ cosine VSS VSS cosine SMx2VSS cosine cosine VSS : 0xFE 0xFF 1) 256/256 (continuously high) is not available. 20.3. Principle of Operation For the effect of CPU clock modes on the operation of this module refer to section "CPU and Clock System" (see Table 4-1 on page 41). value of 4 MHz is recommended, resulting in a pulse width modulator cycle frequency of 4 MHz / 256. Some H-Ports may receive the output signals either of the SMM module or of PWM modules as an alternative. Refer to Table 20-4 for the necessary settings. Refer to section "HW Options" for details. 20.3.1. Hardware settings Prior to entering active mode, the fSM input clock has to be set by HW option (see Table 20-4 on page 136). A frequency Micronas Feb. 10, 2005; 6251-579-1DS 135 CDC 32xxG-C 20.3.2. Initialization Prior to entering active mode, proper SW initialization of the H-Ports assigned to function as H-bridge outputs SMxn+ and Table 20-4: Unit-specific settings Contr. Unit SMA SMB SMC SMD SME SMF SMG All SMG/PWM selection Input clock selection PM.H0 SM SME/PWM selection PM.H7 HW Options Item Address Initialization Item SMAn+/- outputs SMBn+/- outputs SMCn+/- outputs SMDn+/- outputs SMEn+/- outputs SMFn+/- outputs SMGn+/- outputs Setting H4.0 to H4.3 special out H3.0 to H3.3 special out H2.0 to H2.3 special out H5.0 to H5.3 special out H7.0 to H7.3 special out H1.0 to H1.3 special out H0.0 to H0.3 special out DATA SHEET SMxn- has to be made (Table 20-4). The H-Ports have to be configured special out. Refer to "Ports" for details. Enable Bit SR0.SM 20.3.3. Operation After reset, the SMM is in standby mode (inactive). The output lines to the H-Ports are low. For entering active mode, set bit SR0.SM. The FRC will immediately start counting but the control units' output lines will still be low. 20.3.3.1. Generating Output After entering active mode, the SMM's control units are ready to receive sine, cosine and quadrant values. First load the unit/quadrant information to register SMVC, then the cosine value to register SMVCOS and at last the sine value to register SMVSIN. Upon writing SMVSIN, the scheduler logic will set flag SMVSIN.BUSY and load the buff- ered values to the respective unit's sine, cosine and quadrant registers on the next zero transition of the FRC, after a maximum of 256 fSM input clock cycles. After completing the download, flag BUSY is reset and the respective unit will immediately start producing the output signals with the desired timing (see Table 20-3) on the proper pins (see Table 20-2). The above procedure for loading values to a first unit is repeated for all others. Make sure that the BUSY flag is 0 before rewriting registers SMVC, SMVCOS and SMVSIN. 20.3.4. Inactivation Returning the SMM module to standby mode by resetting bit SR0.SM will immediately halt the FRC, return all output signals to 0 and reset all internal registers. 20.4. Rotor Zero Position Detection (RZPD) In addition to the above descriptions, this module supports the rotor zero position detection by supplying motor blockage information. The rotor zero position detection capability is protected by a patent belonging to Siemens VDO Automotive (SV), and may only be used with SV's prior approval. detection in all cases where the CPU has lost track of the display angle of a pointer that is driven by the motor via a mechanical transmission. Furthermore, the rotor zero position detection clock has to be set by HW option (see Table 20-5 on page 137). 20.4.2. Registers 20.4.1. Functional Description Each control unit contains circuitry to detect an induced voltage resulting from the rotation of the connected motor's rotor (Fig. 20-3). A comparator compares the input voltage from one of the unit's H-Ports to 1/9th of the supply voltage. A capture logic opens a capture window and samples the comparator output. The capture result signal supplies a rotor blockage information necessary for the rotor zero position SMVCMP 7 r/w x x SMM Comparator Register 6 5 ACRD 0 4 ACRB 0 3 ACRG 0 2 ACRE 0 1 ACRC 0 0 ACRA 0 Res ACRF 0 136 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C During rotor zero position detection one of a unit's H-Ports (Table 20-4) has temporarily to be operated as input to an internal analog comparator. Reconfigure this port as special input and select this port by register SMVMUX.x. Refer to "Ports" for details. Reading of the induced voltage at the measured motor winding is started by setting the questioned unit's control bit SMVCMP.ACRx to 1. The respective analog comparator's output will now be sampled. Once three consecutive `1' samples (spaced 1/fRZP) - indicating a sufficient analog comparator input voltage - are received, a 1 may be read from the questioned unit's result flag SMVCMP.ACRx, indicating that the rotor zero position detection is under way. Resetting the questioned unit's control bit SMVCMP.ACRx to 0 stops the sampling and resets the result flag. When after a restart of the above sampling procedure and after a sufficiently long capture period still no 1 was read from the questioned unit's result flag SMVCMP.ACRx, this indicates that rotor zero position detection is complete. Parallel rotor zero position detection on all control units is permitted. After completion of rotor zero position detection, reconfigure the comparator input port as special out. ACRA to G r0: r1: w0: w1: Analog Comparator Control and Result for SMA to SMG Capture result: no induced voltage detected Capture result: induced voltage detected Stop capture and clear result flag Start capture SMVMUX 7 r/w r/w E B SMM Multiplex Register 6 5 x C 0x0000 4 x 3 D F 2 1 A G 0 1 0 Res A to G Multiplexer for SMA to SMG r/w0 to 3: Select SMx-COMP input 0 to 3 Never switch a multiplexer during the detection process. 20.4.3. Principle of Operation The RZPD can only be operated together with the stepper motor module. Switching SR0.SM connects/disconnects the comparators from supply and resets all registers. Table 20-5: RZPD-specific settings Contr. Unit SMA SMB SMC SMD SME SMF SMG All Rotor Zero Position Detection Clock RZPC HW Options Item Address Initialization Item Enable Bit Setting H4.0 to H4.3 special in H3.0 to H3.3 special in H2.0 to H2.3 special in H5.0 to H5.3 special in H7.0 to H7.3 special in H1.0 to H1.3 special in H0.0 to H0.3 special in SR0.SM SMA-COMP inputs SMB-COMP inputs SMC-COMP inputs SMD-COMP inputs SME-COMP inputs SMF-COMP inputs SMG-COMP inputs Micronas Feb. 10, 2005; 6251-579-1DS 137 CDC 32xxG-C DATA SHEET H4.0 H4.1 SMA-COMP H4.2 H4.3 H3.0 H3.1 SMB-COMP H3.2 H3.3 H2.0 H2.1 SMC-COMP H2.2 H2.3 H5.0 H5.1 SMD-COMP H5.2 H5.3 H7.0 H7.1 SME-COMP H7.2 H7.3 H1.0 H1.1 SMF-COMP H1.2 H1.3 H0.0 H0.1 SMG-COMP H0.2 H0.3 0 1 Mux 2A 3 0 1 Mux 2B 3 0 1 Mux 2C 3 0 1 Mux 2D 3 0 1 Mux 2E 3 0 1 2 3 0 1 Mux 2G 3 Mux F RZPC HW Option fRZP SMA 0 Debouncer and measurement window R S Result latch + - + - SMB 4 + - SMC 1 + - SMD 5 + - SME 2 + - SMF 6 + - SMG 3 SMVMUX SR0.SM HVDD0 8R R xFDBGECA 6543210 SMVCMP HVDD2 HVDD1 HVDD3 Fig. 20-3: Block diagram of rotor zero position detection circuit 138 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 21. LCD Module The liquid crystal display (LCD) module is designed to directly drive a 1:4 multiplexed liquid crystal display. It generates all signals necessary to drive 4 backplane and 48 segment lines which are output via U-Ports in LCD mode. Up to 192 segments or pixels can be controlled if all U-Ports are designated as segment outputs. In addition, the module provides functions that enable the user to cascade it with external expansion ICs providing more segment lines. It can be operated as master or slave in such an extended system. Features - 1:4 multiplex - 5 V supply - Maximum of 192 segments - Cascadable with external expansion ICs - 0.3 mA buffered 1/3 and 2/3 voltage divider - Zero standby current - 200 A no load active current - Frame frequency HW Option selectable 21.1. Principle of Operation 21.1.1. General Each LCD pixel or segment which is controlled by the LCD module is located at the crossing point of a segment line and a backplane line. The LCD module co-ordinates the output sequences of backplane and segment lines (see Fig. 21-3 on page 141). BP3 SEGn-1 BP2 BP1 BP0 21.1.2. Hardware settings The LCD frame frequency is settable by HW option LC. The resulting frame frequency is the selected input frequency, divided by 120. It should be in the range from 50 to 200 Hz. For best electromagnetic interference results it is recommended to operate all segment and backplane U-Ports in Port Slow mode. Refer to "Ports" for more details and to "HW-Options" for setting the corresponding HW options. Set flag PSLW in register SR0 to HIGH to enable Port Slow mode. SEGn 21.1.3. Initialization After reset, the LCD module is in standby mode (inactive) and all U-Ports are in Port mode, non-conducting. All U-Ports designated to function as backplane or segment outputs are to be set to LCD mode. Refer to "Ports" for more details. This will set these U-Ports to output LOW state. After reset the content of the segment registers is undefined. It must be set by writing the desired segment information to the segment registers and by validating it by a write access to register ULCDLD (write 0x00 for master mode, 0xFF for slave mode), before the LCD module is enabled. SEGn+1 Fig. 21-1: Segments and backplanes A segment pin can drive 4 different voltage levels (UVSS, 1/3 UVDD, 2/3 UVDD, UVDD) in LCD mode. The output of each segment pin is controlled by the corresponding segment bits of the registers UxD, UxTRI, UxNS and UxDPM (further called segment registers). Each such register contains one bit (of a 4 bit segment field) for each of its port pins. Each segment bit (0 to 3) of a segment field corresponds to a backplane line (BP0 to BP3). If the segment bit, corresponding with the backplane line BPx is true, then the segment at the crossing of the two lines is on (black). The LCD module does not contain a display ROM translating character information into segment code. The advantage is that arbitrary characters or displays can be generated just by changing the program code. Segment information is directly entered by writing to the corresponding segment bit. It is validated (loaded to all corresponding slave registers) for all segment U-Ports simultaneously by a write access to register ULCDLD. Two internal voltage sources provide the U-Port circuits and the backplane generator with the voltage levels 1/3 UVDD and 2/3 UVDD. These levels are generated by a buffered resistor divider. 21.1.4. Operation For entering active mode, set flag LCD in register SR0. Each segment and backplane U-Port will immediately start producing its LCD output signal according to the segment information provided during initialization. During active mode, a new segment information is entered by simply writing the desired segment information to the segment registers and by validating it by a write access to register ULCDLD (write 0x00 while in master mode, 0xFF while in slave mode). Each segment and backplane U-Port will immediately start producing an LCD output signal according to the new segment information. Returning the LCD module to standby mode by resetting flag LCD in register SR0 will immediately return all segment and backplane U-Ports to the output LOW state. Micronas Feb. 10, 2005; 6251-579-1DS 139 CDC 32xxG-C DATA SHEET HW Option HW Option fCLK LCD-CLK-IN LCD-CLK-OUT 0 LCD-SYNC-IN LCD-SYNC-OUT 1 1/1 1/1.5 1/2.5 0 1 ULCDLD.LCDSLV SR0.LCD 1/15 8 x frame frequency 3 1 overflow reset 8 State Counter wr ULCDLD load U0D.SG0_0 U0TRI.SG0_1 U0NS.SG0_2 U0DPM.SG0_3 U0D.SG1_0 U0TRI.SG1_1 U0NS.SG1_2 U0DPM.SG1_3 UVDD 2/ 3UVDD 1/ UV 3 DD UVSS U0MODE.L0 Analog Switch and Segment Driver 1 U0.0 U0MODE.L1 Analog Switch and Segment Driver 1 U0.1 U8D.SG5_0 U8TRI.SG5_1 U8NS.SG5_2 U8DPM.SG5_3 U8MODE.L5 Analog Switch and Segment Driver 1 U8.5 Backplane Generator UVDD SR0.LCD en + + LCD Supply 2 /3UVDD 1 /3UVDD 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 U4MODE.L0 Analog Switch and 0 Backplane Driver 1 U4.0 Analog Switch and 1 Backplane Driver 1 U4.1 Analog Switch and 2 Backplane Driver 1 U4.2 Analog Switch and 3 Backplane Driver 1 U4.3 Fig. 21-2: Block diagram For the effect of CPU clock modes on the operation of this module refer to section "CPU and Clock System" (see Table 4-1 on page 41). During power-saving mode the LCD logic is switched off, the port outputs are held at low level but the port register contents will be preserved. provide phase and frequency synchronism for the LCD frame among the cascaded ICs. For master mode, set flag LCDSLV in register ULCDLD LOW. The module always directs signal LCD-SYNC-OUT to pins U8.5 and LCD-CLK-OUT to pins U8.3. They connect to external slave ICs' SYNC-IN and CLK-IN inputs for synchronization. For slave mode, set flag LCDSLV in register ULCDLD HIGH. Configure pins U8.4 and U8.2 to receive signals LCD-SYNCIN and LCD-CLK-IN from an external master IC's SYNC- 21.1.5. Cascading of LCD Driver Modules For expansion purposes, the LCD module may be cascaded with external LCD driver ICs. Master or slave mode is selectable for the LCD module while in standby. Special signals 140 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Starting up and shutting down such an expanded system is described in section 21.3. OUT and CLK-OUT outputs. These signals will then substitute the LCD module's own HW option frame frequency settings. 1 Frame VDD 2/3 BP0 1/3 0 Segment off Segment on BP1 Backplane BP2 BP3 Pin Segment Data Latches U0D.SG0_0 = 0 U0TRI.SG0_1 = 0 U0NS.SG0_2 = 0 U0DPM.SG0_3 = 0 SEG0.0 SEG0.1 U0D.SG1_0 = 0 U0TRI.SG1_1 = 0 U0NS.SG1_2 = 0 U0DPM.SG1_3 = 1 SEG0.2 U0D.SG2_0 = 0 U0TRI.SG2_1 = 1 U0NS.SG2_2 = 1 U0DPM.SG2_3 = 0 SEG0.3 U0D.SG3_0 = 0 U0TRI.SG3_1 = 1 U0NS.SG3_2 = 0 U0DPM.SG3_3 = 1 SEG0.4 U0D.SG4_0 = 1 U0TRI.SG4_1 = 1 U0NS.SG4_2 = 1 U0DPM.SG4_3 = 1 Fig. 21-3: Frame timing diagram A segment at a crossing of backplane and segment lines turns black when the backplane driver outputs a full swing and the segment driver outputs a full swing of opposite polarity at the same time. Micronas Feb. 10, 2005; 6251-579-1DS 141 CDC 32xxG-C 21.2. Registers Please refer to section "Universal Port Registers" for details on segment register layout. DATA SHEET A write access to this memory location simultaneously loads all segment information of all U-Ports in LCD mode to the display. ULCDLD 7 w LCDSLV 0 Universal Port LCD Load Register 6 x 0 21.2.1. Special Register Layout of U-Port 4 U4.0 to U4.3 provide backplane signals in LCD Mode. To operate any ports as LCD segment driver it is necessary to switch all these ports to LCD mode. This has to be done by setting flags U4MODE.L0 through U4MODE.L3. As backplane ports U4.0 to U4.3 require no segment data setting, SG0_0 through SG3_3 bits are not available in U4 registers. 5 x 0 4 x 0 3 x 0 2 x 0 1 x 0 0 x 0 Res LCDSLV LCD Module is Slave Select the mode of the LCD module. w1: LCD module is slave. w0: LCD module is master. 21.3. Application Hints for Cascading LCD Modules 21.3.1. Power On and Start Up Procedure 1. The SW in master and slave configures the corresponding IC. lag between write accesses to ULCDLD of the master and of the slave is kept as small as possible. Suggestion: Lower ms range or customer specification. Table 21-1: Suggested sequence Master Load LCD display register. Clear flag LCDSLV. LCD-CLK-OUT, and LCD-SYNC-OUT: Configure universal ports as Special Out Ports. Slave Load LCD display register. Set flag LCDSLV. LCD-CLK-IN, and LCD-SYNC-IN: Configure universal ports as Special In Ports. 21.3.3. Power Off Procedure 1. (Optional) The processor which decides that the display is to be switched off signals this to the other via IPI. 2. The slave continuously scans the inputs LCD-CLK-IN and LCD-SYNC-IN for the bit combination "11" (SW debouncing required). 3. The master LCD module is switched off. LCD-CLK-OUT and LCD-SYNC-OUT switch to "11". 4. The slave CPU detects the bit combination "11" and immediately switches off the slave LCD module. Note: Keep time delay as short as when switching on. 2. Optionally the slave signals to the master via handshake link or an inter-processor interface (IPI) that it is ready to display. 3. The slave continuously scans the inputs LCD-CLK-IN and LCD-SYNC-IN for the bit combination "01" (SW debouncing required). 4. The master LCD module is switched on. LCD-CLK-OUT and LCD-SYNC-OUT switch to "01". 5. The slave CPU detects the bit combination "01" and immediately switches on the slave LCD module. The slave LCD now generates a display. Note: During the time that the slave needs to detect the bit combination "01", master and slave operate asynchronously. Suggestion: limit time to approximately 100 to 200 ms. 6. The LCD modules now operate in controlled synchronization. 5. All LCD ports output a low signal now. The LCD display is now inactive. 21.3.2. Operation In order to obtain optimum synchronization of LCD switchover, a change of display must be coordinated between master and slave (preferably via IPI) in such a way that the time 142 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 22. DMA Controller The DMA controller allows transferring data fields between internal memory and either an external IC via U-Ports (GBus), or an SPI module, with minimum CPU interaction. DMA transfers can be triggered by the interrupt source output of the corresponding module (self-timed), a dedicated DMA timer output or a port interrupt. The G-Bus is intended to support the operation of external LCD driver ICs (e.g., SED1560 by Epson): The DMA module copies 8-bit pixel data bytes by direct memory access (DMA) to the external IC's graphic RAM with help of that IC's internal autoincrement address counter, and without CPU interaction. Other off-chip registers, allowing control of the display behavior (blinking, scrolling, etc.), have to be addressed by CPU operations. In SPI mode, the DMA module copies data bytes by direct memory access (DMA) to the SPIxD data register, self-timed or under timing of the DMA timer and without CPU interaction, to construct long serial data transfer sequences. It frees the CPU of repeatedly reloading data, e.g. under interrupt control. Features - 3 DMA channels: direct 8-bit data read or write between memory and UPorts U5 and U7 (G-Bus), direct 8-bit data read or write between memory and SPI0, direct 8-bit data read or write between memory and SPI1 - 256 byte maximum DMA block size - one byte DMA block alignment - CPU cycle steal - Interrupt on DMA sequence finished 22.1. Functions The DMA Controller contains one DMA channel logic for each DMA channel, the priority encoder, the control logic, the DMA vector base register, address and cycle count buffer, and the bus interface (see Fig. 22-2 on page 144). CPU ICU The DMA vector base register points to the beginning of the DMA table which is filled with a DMA vector for each DMA channel. Location zero contains the default vector and is not assigned to any DMA channel. Each DMA vector is composed of a 24-bit source/destination address and an 8-bit cycle counter value (see Fig. 22-5 on page 145). A DMA cycle is divided into a sequence of three steps: 1. Output Address of the DMA vector and read source/destination address and cycle counter. 2. Output Address of the DMA vector and write back incremented source/destination address and decremented cycle counter. 3. Output source/destination address and write/read data to/ from I/O module. I/O-Module Each step is one bus access which holds the CPU (cycle stealing). The DMA controller generates the necessary control signals for above bus accesses. An I/O module requests a DMA cycle via its interrupt source output which is connected to the DMA request input (DREQ) of the corresponding DMA channel logic. The DMA interrupt output (DINT) is connected to the ICU instead, where it indicates the end of a DMA sequence (see Fig. 22-3 on page 145). The signal DINT is connected to the G-Bus logic too, where it sets a flag indicating the end of the DMA sequence (see Fig. 22-4 on page 145). 3 Bus Controller DMA Controller 3 4 SRAM ROM Flash Fig. 22-1: System block diagram The DMA Controller transfers bytes (8 bit) between I/O modules and memory. One transfer is called a DMA cycle. The transfer of a block of bytes is called a DMA sequence. Micronas Bridge Bridge Feb. 10, 2005; 6251-579-1DS 143 CDC 32xxG-C DATA SHEET DREQx fDMA HW Opt. PINT0 PINT1 DMATx pending SQ R enable DQ R BYPx DINTx to ICU 1 src# 2 3 Priority n Encoder 31 Mux & & DMA Channel Logic TRIGx ENx DACKx Once per DMA channel fSYS DWAIT Memory Controller & DMA Control Logic A<23:0> D<31:0> MAS<0> MAS<1> nRW D<31:0> DMA Vec. Base LOCK DACC DACK Fig. 22-2: DMA controller The DMA channel logic contains an input multiplexer which selects one of four possible DMA request sources (see Table 22-2 on page 146). The output of this multiplexer sets a pending flag which is automatically reset when the DMA cycle is finished. An enable flag (EN) masks the pending flag output to the priority encoder. A bypass flag (BYP) allows to redirect DREQ to DINT and thus generate no DMA request but an interrupt. The priority encoder assigns each DMA channel a fixed unique priority (Table 22-1). This is necessary when more than one DMA channel signals a DMA request at the same time. The priority encoder outputs the source number with the highest priority. The control logic controls the above described three steps of bus accesses and generates the DMA acknowledge signal (DACKx) which indicates to the requesting module that the DMA transfer has finished. Table 22-1: DMA channels Priority (=Channel No.) 0 1 2 3 I/O-Module Default U-Port SPI 0 SPI 1 GD SPI0D SPI1D Register Name There are two fundamentally different modes to operate DMA sequences. - Self-timed mode describes the situation where the corresponding I/O module requests a DMA transfer when it is ready. In this case the I/O module starts the DMA module when there is something to transfer and the DMA controller starts the I/O module after the transfer is finished. This is the fastest possible way to transfer information via DMA. Trying to get it faster enforces the danger that one of the communication partners is not ready. - Externally triggered mode describes the situation where a third party requests a DMA transfer. This can be a DMA timer or a port interrupt. The SW design has to guarantee that the I/O module as well as the DMA controller can do their work between two consecutive DMA requests. 144 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C SPIx Int Src start SPIx DMA DREQx DACKx DINTx rd ICU 00C 008 004 000 32 Bit DMA Vector 3 DMA Vector 2 DMA Vector 1 Default DMA Vector Base + DMA Channel * 4 DMA Vector Base SPIx 1 & rd SPIxD 8-bit count 24-bit DMA Block Addr. nRW & wr SPIxD 7 6 5 4 3 2 1 0 Data Data Data Data Data Data Data Data Fig. 22-3: DMA SPI interaction GBus DREQ1 DACK1 DINT1 DMA DREQ1 DACK1 DINT1 rd ICU GBus Fig. 22-5: DMA vector table 1 & rd GD nRW & wr GD Fig. 22-4: DMA port interaction 22.2. Registers The DMA registers can be read or written 32-bit wide, asynchronous and without wait states. DE DMA Enable r/w1: enable DMA controller r/w0: disable DMA controller Enables the DMA controller clock (fSYS) and the clock for all DMA Timer (fDMA). Before setting to 0, make sure that all individual DMA channels are terminated. SRC r31-0: Priority source output The number of the highest pending and enabled DMA request. DVB 7 r/w r/w r/w r/w A7 0 0 DMA Vector Base 6 0 5 0 4 0 3 0 2 0 1 0 0 0 3 2 1 Offs A23 to A16 A15 to A8 0 0 0x0000 0 0 0 0 DCxM 0 DMA Channel x Mode Register 6 5 DMAT x x x BYP 0x0000 DIR 7 Res r/w r/w P EN 4 3 2 TRIG 1 0 1 MAS 0 Offs DST 7 r/w DE DMA Status Register Res 6 x 5 x 4 3 2 SRC 1 0 0 Offs 0x00 Res P r1: r0: w1: w0: DMA Pending DMA transfer pending No DMA transfer pending No action Clear P Micronas Feb. 10, 2005; 6251-579-1DS 145 CDC 32xxG-C DMAT r/w7-0: DMA Timer DMA timing, equation: EN r1: r0: w1: w0: BYP r/w1: r/w0: DIR r/w1: r/w0: MAS r/w3: r/w2: r/w1: r/w0: Enable DMA channel DMA sequence active DMA sequence finished enable DMA channel disable DMA channel DATA SHEET f DMA f DMAT = ---------------------DMAT + 1 2 TRIG r/w15-0: Trigger Source (see Table 22-2) Bypass Interrupt don't bypass DMA-Request to ICU bypass DMA-Request to ICU. DMA Direction write to I/O-module read from I/O-module Memory Access Size reserved 32-bit (not supported) 16-bit (not supported) 8-bit Table 22-2: DMA trigger sources TRIG 3 x x x x 2 x x x x 1 0 0 1 1 0 0 1 0 1 DMA request from I/O-module DMATx PINT0 PINT1 Source 22.3. Principle of Operation The DMA Controller is operable in all CPU modes. However, it has to be disabled (see 22.3.9.) during CPU mode switching to prevent undefined clock system behavior. For correct CPU mode switching, follow the sequence given section 4.2. Start the DMA sequence by writing the first element to be transferred to the data register of the corresponding I/O module and enable the DMA channel. 22.3.4. Self-Timed DMA Read from I/O Operation 22.3.1. Initialization of the DMA Controller The DMA vector table has to be installed starting at a 128 byte aligned address. See figure 22-5 for DMA vector layout. Write the start address of the DMA vector table as a 32 bit address to the DMA Vector Base register (DVB) and note that only bits 7 to 23 may be modified. The other bits are forced to zero. Enable the DMA controller by setting flag DE in the DMA Status register (DST). The input frequency fDMA for all DMA timer can be selected by the register DMAC in the HW Options field. Flag DIR in register DCxM must contain a zero for reading from an I/O module. Write the destination address (24 bit), pointing to the first element, and the block size (8 bit) to the corresponding DMA vector table entry. Start an SPI DMA sequence by writing to register SPIxD of the corresponding SPI module. The data of this write may be omitted. Then enable the DMA channel. Start a graphic bus DMA sequence by reading from register GD. The data of this read may be omitted. Then enable the DMA channel. 22.3.2. Initialization of a DMA Channel All steps necessary to initialize the involved I/O module have to be taken according to the description in the respective chapter. Write the appropriate values to the DMA Channel Mode register (DCxM). Select the trigger source by field TRIG, program the DMA timer by field DMAT if necessary, select transfer direction (DIR) and size (MAS) and set BYP to one. 22.3.5. Externally Triggered DMA Operation The procedure is the same as with the self-timed operation with some distinctions. In both cases (read/write) the SW initiates the first action in the peripheral module. Enable the DMA channel after this module has finished its work. Otherwise a DMA cycle may happen too early, transferring invalid data. It is possible to do externally triggered DMA transfers without the SW initiating the first action. In this case, the maximum block size is limited to 255 byte because the count value in the DMA vector has to be programmed with block size plus one. In a write case (Fig. 22-7), the sequence starts with data D1. In a read case (Fig. 22-8), the first DMA cycle reads invalid data D0. The first element of the transferred block has to be omitted in the latter case. 22.3.3. Self-Timed DMA Write to I/O Operation Flag DIR in register DCxM must contain a one for writing to an I/O module. Write the source address (24 bit), pointing to the first plus one element, and the block size (8 bit) to the corresponding DMA vector table entry. 146 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 22.3.8. Stalling and Termination of a DMA Sequence Clearing the flag DCxM.EN stalls a DMA sequence. Further DMA requests of the disabled DMA channel set the pending flag DCxM.P. Setting the flag DCxM.EN again enables the DMA channel thus continuing the DMA sequence. This mechanism has to be operated carefully because data may be lost during a stall period. A final termination of a DMA sequence can be achieved by first disabling the DMA channel (DCxM.EN=0) and the source of the DMA requests and secondly clearing the pending flag (DCxM.P=0). Do not forget to clear DCxM.BYP if further DMA requests are to generate an interrupt. 22.3.6. End of DMA Sequence The end of the DMA sequence is indicated by the enable flag (EN=0) and an interrupt which calls the ISR of the corresponding I/O module. The address field of the corresponding DMA vector points to the next element after the last transferred element. The counter field is at zero. 22.3.7. Enabling of a DMA Channel Setting the flag EN to one enables the DMA channel. Make sure that there is no pending DMA request at that point of time. Clearing an active pending flag P and enabling the corresponding DMA channel must not be done with a single instruction. This might lead to an unwanted DMA cycle. First clear P and then set EN in two instructions. 22.3.9. Disabling the DMA Controller First terminate all DMA channels (see 22.3.8.) and then clear flag DST.DE. Do not forget to clear DCxM.BYP if further DMA requests are to generate an interrupt. 22.4. Timing Diagrams fSYS DREQx DACC A DMA Vector DMA Vector Adr D Adr Adr++ Data nRW DACKx pending DINTx EN Fig. 22-6: DMA cycle timing Micronas Feb. 10, 2005; 6251-579-1DS 147 CDC 32xxG-C 22.4.1. DMA Sequences SPI DATA SHEET DREQx A,D DACKx SPIwr SPIio counter DINTx pending EN 4 D0 D1 3 D2 2 D3 1 0 CPU D0 DMA D1 DMA D2 DMA D3 Fig. 22-7: SPI write sequence (serial out) DREQx A,D DACKx SPIwr SPIio counter DINTx pending EN 4 D0 D1 3 D2 2 D3 1 0 CPU Start DMA D0 DMA D1 DMA D2 DMA D3 Fig. 22-8: SPI read sequence (serial in) 148 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 22.4.2. DMA Sequences Graphic Bus Interface DREQx A,D DACKx wr GD GDB GWEQ DINTx DTA, EN D0 D1 D2 D3 CPU D0 DMA D1 DMA D2 DMA D3 Fig. 22-9: Graphic bus write sequence (parallel out) DREQx A,D DACKx rd GD GDB GOEQ DINTx DTA, EN D0 D1 D2 D3 CPU Start DMA D0 DMA D1 DMA D2 DMA D3 Fig. 22-10: Graphic bus read sequence (parallel in) The final DMA request pulse clears the DMA Transfer Active (DTA) flag, in addition to generating an interrupt. Micronas Feb. 10, 2005; 6251-579-1DS 149 CDC 32xxG-C DATA SHEET 150 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 23. Graphic Bus Interface The graphic bus interface (GB) is intended to support the operation of external LCD driver ICs (e.g., SED1560 by Epson). Features - DMA read/write to external device - CPU read/write to external device - Read/write timing generation - Read/write control signals generation 23.1. Functions The DMA module copies 8-bit pixel data bytes by direct memory access (DMA) to the external IC's graphic RAM with help of that IC's internal autoincrement address counter, and without CPU interaction. Other off-chip registers, allowing control of the display behavior (blinking, scrolling, etc.), have to be written and read by CPU operations. the CPU. Please refer to section DMA for information on GB DMA interaction. The register GD provides the data interface for the GB. Writing to GD outputs the data byte at U5.0 to U5.3 (low nibble) and U7.4 to U7.7 (high nibble). Reading from GD inputs a data byte from above pins. The assignment to external signals is shown in table 23-1. fIO D wr GD rd GD DACKx DINTx DREQx nRW Graphic Bus Interface GOEQ GWEQ GD0 to7 Table 23-1: Port assignment Port U5.0 : U7.7 1) U6.2 Name GDB0 : GDB7 GADB GWEQ GOEQ External address bus External write signal External read signal External data bus Fig. 23-1: Port bus block diagram The necessary timing is done autonomously by the GB logic. Any U-Port may be used as address output port operated by U6.1 1) Any U-Port may be used as address output port. 23.2. GB Registers GD 7 r/w Graphic Bus Data Register 6 5 4 Data 0x00 GC 0 0 Res Offs r/w Graphic Bus Control Register 7 6 TIM 0x00 3 2 1 5 4 3 E 2 BSY 1 SEQ 0 DTA 0 Offs Res A write access to this register generates the DACK signal and writes to registers UxD. A read access to this register generates the DACK signal and reads from registers UxPIN. TIM w15-1: GB Timer GB timing, equation: 2 TIM + 1 t GB = ----------------f IO w0: GB logic is disabled, clock input is disabled Micronas Feb. 10, 2005; 6251-579-1DS 151 CDC 32xxG-C E r/w1: r/w0: Enable Enable timing generation Disable timing generation DATA SHEET Every DACKx or access to GD signal sets this flag and the DINTx signal clears it again. DTA DMA Transfer Active r1: DMA sequence started r0: DMA sequence is finished w1: Set DTA w0: No action This flag indicates the end of a DMA sequence. It has to be set by SW before a DMA sequence is started. It is cleared by signal DINTx. BSY Busy r1: GB timing is active r0: GB timing is not active Every DACKx signal or access to GD sets this flag and every DREQx signal clears it again. SEQ r1: r0: DMA Sequence DMA sequence is active DMA sequence is not active 23.3. Principle of Operation 23.3.1. Initialization Table 23-2 shows the necessary settings of the port configuration registers. not finished and read the register GD. The DMA Controller reads the remaining bytes from register GD and generates an interrupt when finished. DTA low marks the end of the DMA sequence. 23.3.2.3. CPU Write Access Writing the byte to register GD is sufficient. The end of the transfer is indicated by flag BSY. 23.3.2.4. CPU Read Access The read access must be initiated by a dummy read access to register GD. After BSY is low the desired byte can be read from register GD. This last step automatically initiates the next read timing of the GB logic. If this is not desired, because GOEQ stays active until the next access to GD, after BSY becomes low, first disable the GB timing generation by clearing flag E in register GC and then read register GD. Table 23-2: Port configurations Register U5MODE, U7MODE, U6MODE U5NS, U7NS U6NS U5TRI, U7TRI, U6TRI Setting 0x00 Mode Port mode 0x00 0x06 0x00 Normal Special Out Enable the timing generation by setting flag E in register GC. Enable the clock input and select the desired timing of the control signals GOEQ and GWEQ in the field GC.TIM. The minimum high time of the control signals is one fIO cycle. 23.3.3. Inactivation Inactivation is easily done by writing GC.TIM to zero. Make sure not to switch off the GB as long as a transfer is active (DTA or SEQ or BUSY are set). 23.3.2. Data transfer Data to/from an external device can be transferred directly by CPU access or, especially for bigger amounts of data and with help of the external device's autoincrement address counter, a DMA sequence can be started. Make sure not to start a GB transfer unless the flags DTA, SEQ and BSY are zero. 23.3.2.1. DMA Write Sequence After initialization of the corresponding DMA channel, set flag DTA to show others that a DMA sequence was initiated but not finished and write the first value to be transferred via the GB to the register GD. The DMA Controller writes the remaining bytes to register GD and generates an interrupt when finished. DTA low marks the end of the DMA sequence. 23.3.2.2. DMA Read Sequence After initialization of the corresponding DMA channel, set flag DTA to show others that a DMA sequence was initiated but 23.3.4. Precautions A write to register GD alters the universal ports data latches U5D and U7D even if the GB is disabled (GC.TIM = 0). 152 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 23.3.5. Timings DREQx A,D DACKx Enable tGB Count (fIO) GDB tWDS GWEQ tWH DTA 1) D1 tWDH D2 A A++ D1 A A++ D2 Fig. 23-2: DMA write (parallel out) DREQx A,D DACKx Enable tGB Count (fIO) GDB GOEQ tRH DTA 1) D2 tACC D3 A A++ D2 A A++ D3 Fig. 23-3: DMA read (parallel in) 1) DTA at the end of the last DMA cycle. tWDS: Write data setup time tWDH: Write data hold time tWH: DMA write high time tRH: DMA read high time tACC: Read access time tGB: GB time DACKx can be replaced by write to GD or read from GD if direct CPU access is desired. The signals "enable" and "count" are internal signals. Micronas Feb. 10, 2005; 6251-579-1DS 153 CDC 32xxG-C DATA SHEET 154 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 24. Serial Synchronous Peripheral Interface (SPI) A SPI module provides a serial input and output link to external hardware. An eight or nine bit data frame can be transmitted in synchronism to an internally or externally generated clock. The SPI module can be operated via direct access or via DMA. The number of SPIs implemented is given in Table 24-1. The "x" in register names distinguishes the module number. Features - 8 or 9-bit frames - Internal or external clock - Programmable data valid edge - Programmable clock polarity - Three internal clock sources programmable - Input deglitcher for clock and data - DMA interface SPIx-D-IN SI 1 0 HW Option 0 Deglitcher 1 1 0 shift in 1 SPIx-D-OUT SO 1 0 0 shift out 8 1 HW Option 1 RXSEL BIT8 INTERN 7 6 5 4 3 2 SPIxD 1 0 Deglitcher 7 LEN9 3xT0 SPIxM 6 5 4 3 2 1 0 SPIx Interrupt Source Scheduler clk 1 SR0.SPIx 0 SPIx-CLK-OUT SO clkout 1 2 1 SPIx-CLK-IN SI Deglitcher 1 0 1 HW Option HW Option extclk 0 F0SPI F1SPI F2SPI 1 0 CSF0/1 1/1 3:1 MUX 1/1,5 1/2,5 intclk 1 INTERN 2 Fig. 24-1: Block diagram Micronas shift clock Feb. 10, 2005; 6251-579-1DS 155 CDC 32xxG-C 24.1. Principle of Operation 24.1.1. General An SPI serves as an 8 or 9-bit wide input/output shift register. Either an internally or an externally generated clock can be used to shift data in and out. The input SPIx-D-IN is connected to the LSB of the shift register. The output of the shift register is connected to output signal SPIx-D-OUT. Thus each time a frame is transmitted by shifting bits out, bits are shifted in simultaneously and vice versa. Deglitchers in the data and clock input paths are active only in external clock mode. The input and output can be inverted by HW Option. If the deglitcher is active, input changes polarity after three consecutive samples have shown the same new polarity. Thus, a delay of three oscillator clock cycles is introduced. This feature imposes a limit on the maximum transmission frequency. The interrupt is generated after the last bit is clocked out. The interrupt source output of this module is routed to the Interrupt Controller logic. But this does not necessarily select it as input to the Interrupt Controller. Check section "Interrupt Controller" for the actually selectable sources and how to select them. For the effect of CPU clock modes on the operation of this module refer to section "CPU and Clock System" (see Table 4-1 on page 41). DATA SHEET Table 24-1: Module specific settings Module HW Options Initialization Name Item Address Item Setting All SPIs F0SPI clock F1SPI clock F2SPI clock SPI0 D in inversion D out inversion Prescaler SP0C SPI0-D- U3.5 IN special input in SPI0-D- U3.6 special OUT out output SPI0CLK-IN input SPI0CLKOUT output SPI1 D in inversion D out inversion Prescaler SP1C U3.4 special in U3.4 special out SR0. SPI1 SR0. SPI0 SP2C SP1C SP0C Enable Bit SP0C SMC 24.1.2. Hardware settings Clock frequency settings and the polarity of the data connections of the SPIs are settable by HW Options (Table 24-1). Refer to "HW Options" for setting them. 24.1.3. Initialization After reset, a SPI is in standby mode (inactive). Prior to entering active mode, proper SW configuration of the U-Ports assigned to function as data in- or outputs and clock in- or outputs has to be made (Table 24-1). Refer to "Ports" for details. For entering active mode of a SPI, set the respective enable bit (Table 24-1). Prior to operation, the desired clock frequency and telegram length have to be selected. 24.1.3.1. Clock Source The SPI can be operated as clock master, using an internally generated clock, or as clock slave, using an externally generated clock. The flag INTERN must be set in the SPIxM Mode register to operate the SPI as clock master. There are several options for selection of the internal clock. Each input of a 3-to-1 multiplexer can be programmed by HW Options to a different frequency. These three input frequencies F0SPI, F1SPI and F2SPI are used for all SPIs. The output of the 3-to-1 multiplexer is programmed by way of clock selection field (CSF) in register SPIxM. This clock can be used as shift clock directly, inverted and divided by 1.5 or 2.5. The shift clock is output by signal SPIx-CLK-OUT. f0 can be selected as maximum clock speed in this operation mode. SPI1-D- U4.0 special IN in input SPI1-D- U4.1 OUT special output out SPI1CLK-IN input SPI1CLKOUT output U3.7 special in U3.7 special out SP1C SMC If flag INTERN is zero, the SPI operates as clock slave and an externally generated clock is used. The external clock is input by signal SPIx-CLK-IN. This clock must not exceed 1.1 MHz. The polarity and the sampling edge of the clock is defined by field SCLK in register SPIxM. 24.1.3.2. Telegram Length Flag LEN9 in register SPIxM defines the length of a transferred frame. The ninth bit of the shift register is read or written at the location of flag BIT8 in register SPIxM. 156 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 24.1.5. Inactivation Returning a SPI module to standby mode by resetting its respective enable bit (Table 24-1) will immediately terminate any running receive or transmit operation and will reset all internal registers. 24.1.4. Operation 24.1.4.1. Transmit Mode Transmission is initiated by a write access to data register SPIxD. The SPI will immediately begin transmitting the selected number of data bits out from its shift register, in synchronism with the selected clock. A write access during a transmission is ignored. The frame is transmitted MSB first. In nine-bit mode flag BIT8 is MSB of the shift register (Fig. 24-2 to 24-5). At the end of the frame, an interrupt source signal is generated which may be selected to trigger an interrupt. 24.1.4.2. Receive Mode The receive mode must be activated by a write access to register SPIxD. The SPI will immediately begin clocking in the selected number of data bits into its shift register, in synchronism with the selected clock. At the end of the frame, an interrupt source signal is generated which may be selected to trigger an interrupt. 24.1.4.3. DMA Please refer to section "DMA" for information on the operation of the SPI in DMA mode. 24.1.6. Precautions A single wire bus is easiest implemented by a wired-or configuration of the SPIx-D-OUT output port and the open drain output of the external transmitter: simply configure the SPIx-D-OUT output port in Port Slow mode, always operate it in Port Special Output mode and connect it directly to the external open drain output. An external pull-up resistor is not necessary in this configuration because the SPIx-D-OUT output port supplies the necessary pull-up drive. If the SPIx-D-OUT output port has to be operated in Port Fast mode, this simple scheme is not possible, because the pull-down action of the external open drain output may exceed the absolute maximum current rating of the SPIx-DOUT output port. A discrete external wired-or is recommended for this situation. During operation, make sure that the external clock does not start until after SPIxD has been written, otherwise correct data transfer is not be guaranteed. 24.2. Registers The following registers are available once for SPI0 and SPI1 each. SCLK r/w: Sample Clock Clock polarity and edge of data sampling. (Table 24-2) SPIxD 7 r/w 0 0 SPI x Data Register 6 5 4 3 2 1 0 Table 24-2: SCLK usage SCLK Clock Polarity low Sampling Edge falling rising high rising falling See Fig. Bit 7 to 0 of Rx/Tx Data 0 0 0 0 0 0 Res 1 0 0 0 1 0 1 24-3 24-5 24-2 24-4 SPIxM 7 r/w BIT8 0 SPI x Mode Register 6 LEN9 0 0 1 CSF 5 4 3 SCLK 0 2 0 1 1 RXSEL INTERN 0 0 0 0 0 Res BIT8 Bit 8 of Rx/Tx Data r/w: Rx/Tx data bit. In 8 bit mode (LEN9 = 0) this bit is undefined when read. LEN9 r/w0: r/w1: RXSEL r/w0: r/w1: INTERN r/w0: r/w1: Frame Length 9 Bit Selection 8 bit mode. 9 bit mode. Receive Selection Input active. Low level at input. Internal/External Clock Selection Use external clock. Use internal clock. CSF w: Clock Selection Field Source of internal clock (Table 24-3) Table 24-3: CSF usage CSF 1 0 0 1 0 0 1 x F0SPI F1SPI F2SPI Source of internal clock Micronas Feb. 10, 2005; 6251-579-1DS 157 CDC 32xxG-C 24.3. Timing DATA SHEET wr SPIxD clk out SPIx-D-OUT D8 D7 D6 D5 D4 D3 D2 D1 D0 SPIx-D-IN D8 D7 D6 D5 D4 D3 D2 D1 D0 SPIx Int. Src. Fig. 24-2: Nine-bit frame. Data valid at rising edge. Clock inactive high wr SPIxD clk out SPIx-D-OUT D7 D6 D5 D4 D3 D2 D1 D0 SPIx-D-IN D7 D6 D5 D4 D3 D2 D1 D0 SPIx Int. Src. Fig. 24-3: Eight-bit frame. Data valid at falling edge. Clock inactive low wr SPIxD clk out SPIx-D-OUT D8 D7 D6 D5 D4 D3 D2 D1 D0 SPIx-D-IN D8 D7 D6 D5 D4 D3 D2 D1 D0 SPIx Int. Src. Fig. 24-4: Nine-bit frame. Data valid at falling edge. Clock inactive high wr SPIxD clk out SPIx-D-OUT D7 D6 D5 D4 D3 D2 D1 D0 SPIx-D-IN D7 D6 D5 D4 D3 D2 D1 D0 SPIx Int. Src. Fig. 24-5: Eight-bit frame. Data valid at rising edge. Clock inactive low 158 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 25. Universal Asynchronous Receiver Transmitter (UART) A UART provides a serial receiver/transmitter. A 7-bit or 8-bit telegram can be transferred asynchronously with or without a parity bit and with one or two stop bits. A 13-bit baud rate generator allows a wide variety of baud rates. A two-word receive FIFO unburdens the SW. Incoming telegrams are compared with a register value. Interrupts can be triggered on transmission complete, reception complete, compare and break. The number of UARTs implemented is given in Table 25-1. The "x" in register names distinguishes the module number. Features - Full duplex. - 7-bit or 8-bit frames. - Parity: None, odd or even. - One or two stop bits. - Receive compare register. - Two word receive FIFO. - 13-bit baud rate generator. UAxIF 2 ADR 1 BRK 0 RCVD r 2 ADR UAxIM 1 BRK 0 RCVD w UAxD r UAxCA compare address register w rx FIFO & 3 8 = 8 8 UART Interrupt Source >1 & break rx shift register 2 of 3 rx & received 4 rx control tx control RBUSY EMPTY TBUSY OVRR BRKD FRER PAER FULL tx shift register r w tx 1 tx 7 7 6 6 5 5 4 4 3 3 STPB 2 2 ODD 1 1 PAR 0 0 LEN UAxD tx data register w UAxC 4 UAxBR1 f0 clk UAxBR0 clk 1/8 fBR fsample 5 bit down cnt zero 8 bit down counter zero Fig. 25-1: Block diagram Micronas Feb. 10, 2005; 6251-579-1DS 159 CDC 32xxG-C 25.1. Principle of Operation 25.1.1. General A UART module contains a receive shift register that serves to receive a telegram via its RX input. A FIFO is affixed to it that stores two previously received telegrams. A transmit shift register serves to transmit a telegram via its TX output. Other features include a receive compare function, flexible interrupt generation and handling, and a set of control, error and status flags that facilitate management of the UART by SW. The interrupt source output of this module is routed to the interrupt controller logic. But this does not necessarily select it as input to the interrupt controller. Check section "interrupt controller" for the actually selectable sources and how to select them. A programmable baud rate generator generates the required bit clock frequency. For the effect of CPU clock modes on the operation of this module refer to section "CPU and Clock System" (see Table 4-1 on page 41). A UART module is only capable to receive telegrams that differ by no more than 2.5% from its own baud rate setting. DATA SHEET 25.1.3. Initialization After reset, a UART is in standby mode (inactive). Prior to entering active mode, proper SW configuration of the U-Ports assigned to function as RX input and TX output has to be made (Table 25-1). The RX port has to be configured as special in and the TX port has to be configured as special out. Refer to "Ports" for details. For entering active mode of a UART, set the respective enable bit (Table 25-1). Prior to operation, the desired baud rate, telegram format, compare address and interrupt source configuration have to be done. 25.1.3.1. Baud Rate Generator The receive and transmit baud rate is internally generated. The baud rate registers UAxBR0 (low byte) and UAxBR1 (high byte) serve to enter the desired 13-bit setting. Write UAxBR0 first, UAxBR1 last. The baud rate generator is a 13-bit down-counter which is clocked by f0. It generates the sample frequency: f0 f sample = -------------------------------------------------------------------------------Value of Baud Rate Registers + 1 Its output frequency fsample is divided by eight to generate the baud rate (bit/second). 25.1.2. Hardware settings The polarity of most RX and TX connections of the UART is settable by HW Options (See table 25-1 and figure 25-2). Refer to "HW Options" for setting them. SR0.UARTx tx f0 clk UARTx HW Option 0 f0 f sample BR = ---------------------------------------------------------------------------------------------- = -------------( Value of Baud Rate Registers + 1 ) x 8 8 UARTx-TX 1 1 SO UARTx-RX 1 1 f0 Value of Baud Rate Registers = ---------------- - 1 BR x 8 0 rx SI HW Option Fig. 25-2: Context diagram 25.1.3.2. Telegram Format The format of a telegram is configured in the control and status register UAxC. A telegram starts with a start bit, followed by the data field. The data field consists of 7 or 8 data bit. There can be a parity bit after the data field. The telegram is finished by one or two stop bits (see Table 25-3 on page 164). 160 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Table 25-1: Module-specific settings Module Name UART0 HW Options Item RX inversion TX inversion UART1 RX inversion TX inversion UA1 Address UA0 Initialization Item UART0-RX input UART0-TX output UART1-RX input UART1-TX output Setting U2.5 special in U2.4 special out U2.3 special in U2.2 special out SR0.UART1 SR0.UART0 Enable Bit UAxIF and can be enabled by setting bits in the interrupt mask register UAxIM. S0 S0 S0 S0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 7 P T0 T1 7 T0 T1 1. When the flag TBUSY in register UAxC is set to zero, the interrupt source output is triggered. This indicates that a transmission is finished and the transmit buffer is empty. There is neither an interrupt flag to indicate this event, nor a mask flag to disable this interrupt. 2. RCVD is generated by the receive control logic at the end of each received telegram even if the FIFO is full. This signal is enabled by setting the corresponding bit in register UAxIM. 3. BRK is generated by the receive control logic each time a break is detected. This signal is enabled by setting the corresponding bit in register UAxIM. 4. ADR is generated by the address comparator. This signal is enabled by setting the corresponding bit in register UAxIM. BRK and ADR also set flags in the interrupt flag register UAxIF when enabled. The first RCVD interrupt, when the FIFO has been empty before, sets a flag in UAxIF too. Even if all interrupts are enabled in register UAxIM, the interrupt source output is triggered only once within a telegram. UAxIF flags remain valid until the end of the next telegram. ADR is not generated and the ADR flag is not set if a frame or parity error was detected in the corresponding telegram. 6 T0 6 7 P T0 S = Start bit P = Parity bit T0 = 1. stop bit T1 = 2. stop bit Fig. 25-3: Examples of telegram formats The level of the start bit is always opposite to the neutral level. The level of the stop bits is always the same as the neutral level. If a parity bit is programmed, odd or even parity can be selected. Table 25-2: Definition of parity bit Parity Flag odd odd even even Number of Ones odd even odd even Parity Bit 0 1 1 0 25.1.4. Operation With proper HW configuration and SW initialization, a UART module is ready to transmit and receive telegrams in the selected format. 25.1.4.1. Transmit A write access to UART Data register UAxD immediately loads the transmit shift register and starts transmission with sending the start bit. The flag TBUSY in register UAxC is set. At the end of transmission the interrupt source signal is triggered and the flag TBUSY is reset. To avoid data corruption, ensure that flag TBUSY is LOW before writing to UAxD 25.1.4.2. Receive A first negative edge of a telegram on the RX line of a UART starts a receive cycle and sets the flag RBUSY in UAxC. After reception of the last bit of the telegram, the telegram content, together with its status information, is transferred to the receive FIFO and an interrupt is generated. RBUSY is resetted. Telegram data are available in register UAxD, telegram status in register UAxC. As a general rule, the parity bit completes the number of ones in the data field to the selected parity. 25.1.3.3. Compare Address The content of the Compare Address register UAxCA is compared with each received telegram. On a match, the interrupt flag ADR is set and the interrupt source signal is triggered. The MSB of register UAxCA must be set to zero if transmission of a seven-bit data field is configured in register UAxC. 25.1.3.4. Interrupt Four signals can trigger the UART interrupt source output. Three of them set their own flags in the interrupt flag register Micronas Feb. 10, 2005; 6251-579-1DS 161 CDC 32xxG-C During reception, the following checks are performed according to the register UAxC setting: 1. A parity error is detected if the parity of the received telegram does not match the programmed parity. The flag PAER in register UAxC is set in this case. Differing telegram length settings in register UAxC and receiver may also cause parity errors. 2. A frame error is detected if the level of start or stop bits violate the transmission rule. The flag FRER in register UAxC is set in this case. 3. A break condition is detected if the receive input remains low for one complete telegram duration. When a break starts during telegram, this condition must extend over another telegram length to be properly detected. This event sets the flag BRKD in register UAxC and can trigger the interrupt source output if enabled. After a break, the receive input must be high for at least 1/4 of the bit length before a new telegram can be received. Telegrams of an external RS232 interface are correctly received, even if they are transmitted without gaps (the start bit immediately follows the stop bit of the preceding telegram). 25.1.4.3. Receive FIFO The receive FIFO is able to buffer the data fields of two consecutive telegrams. But not only the data field of a telegram is double buffered, the related information is double buffered DATA SHEET too. The flags PAER, FRER and BRKD in register UAxC apply to a certain telegram and are thus double buffered. The receive FIFO is full if two telegrams were received but the SW did not yet read register UAxD. If there is a third telegram, it is not written to the FIFO and its data are lost. The flags EMPTY, FULL and OVRR show the status of the FIFO. EMPTY indicates that there is no entry in the FIFO. FULL will be set with the second entry in the receive FIFO and indicates that there is no more entry free. OVRR indicates that there was a third telegram which could not be written to the FIFO. Status flags are readable as long as the corresponding data field was not read from register UAxD. As soon as a FIFO entry is read out, the status flags of this entry are lost. They are overwritten by the flags of the second entry. SW first has to read the flags and then the corresponding FIFO entry. The flags PAER, FRER and BRKD apply to a certain telegram and are only valid if there is at least one entry in the FIFO (EMPTY = 0). The flags EMPTY, FULL and OVRR apply to the FIFO and are valid all the time. 25.1.5. Inactivation Returning a UART module to standby mode by resetting its respective enable bit (Table 25-1) will immediately terminate any running receive or transmit operation and will reset all internal registers. 25.2. Timing The duration of a telegram results from the total telegram length in bits (LTG) (see Table 25-3 on page 164) and the baud rate (BR). L TG t TG = --------BR The incoming signal is sampled with the sample frequency and filtered by a 2 of 3 majority filter. A falling edge at the output of the majority filter starts the receive timing frame for the telegram. An individual bit is sampled with the fifth sample clock pulse within that timing frame (cf. Fig. 25-4 and 25-5). If a bit was the last bit of its telegram, reception of a new telegram can start immediately after this sample. With a receive telegram, interrupt source is triggered and flags are set just after the sample of the last stop bit. With a transmit telegram, interrupt source is triggered and BUSY reset after the nominal end of the last stop bit. 162 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 1 fsample rxdat asynchron 1. sample 2. sample 3. sample start data sample clock 2 3 4 5 6 7 8 startbit bit 0 bit 1 indicates the recognition of the low level of the filtered input signal Fig. 25-4: Start of telegram 1 fsample rxdat asynchron 1. sample 2. sample 3. sample start data sample clock Rx Interrupts Tx Interrupt BUSY 2 3 4 5 6 7 8 1. stopbit 2. stopbit startbit Flags are set Fig. 25-5: End of telegram Micronas Feb. 10, 2005; 6251-579-1DS 163 CDC 32xxG-C 25.3. Registers LEN w0: w1: 1 0 DATA SHEET UAxD 7 r w x x UART x Data Register 6 5 4 3 2 Length of Frame 7bit frame. 8bit frame. Receive register Table 25-3: Telegram format and length Transmit register x x x x x x Res LEN 0 PAR 0 0 1 1 0 0 1 1 STPB 0 1 0 1 0 1 0 1 Format S, 7D, T0 S, 7D, T0, T1 S, 7D, P, T0 S, 7D, P, T0, T1 S, 8D, T0 S, 8D, T0, T1 S, 8D, P, T0 S, 8D, P, T0, T1 LTG 9 10 10 11 10 11 11 12 UAxC 7 r RBUSY 0 w x x UART x Control and Status Register 6 BRKD x x x 0 0 5 FRER x x x 4 OVRR 0 x x 3 PAER x STPB 0 2 EMPTY 1 ODD 0 1 FULL 0 PAR 0 0 TBUSY 0 LEN 0 Res Res 0 1 1 1 1 RBUSY r0: r1: BRKD r0: r1: FRER r0: r1: OVRR r0: r1: PAER r0: r1: Receiver Busy Not busy. Busy. Break Detected No break. Break. Frame Error Detected No error. Error. Overrun Detected No overrun. Overrun. Parity Error Detected No error. Error. UAxBR0 UART x Baud Rate Register low byte 7 w 0 6 5 4 3 2 1 0 Bit 7 to 0 of Baud Rate 0 0 0 0 0 0 0 Res UAxBR1 7 w x - UART x Baud Rate Register high byte 6 x - EMPTY Rx FIFO Empty r0: Not empty. r1: Empty. There is at least one entry present if EMPTY is zero. PAER, FRER and BRKD are not valid if EMPTY is set. FULL r0: r1: Rx FIFO Full Not full. Full. 5 x - 4 3 2 1 0 Bit 12 to 8 of Baud Rate 0 0 0 0 0 Res The Baud Rate Registers UAxBR0 and UAxBR1 have to be written low byte first to avoid inconsistencies. UAxBR0 is the low byte. Valid entries in the Baud Rate Registers range from 1 to 8191. Don't operate the baud rate generator with its reset value zero. TBUSY Transmitter Busy r0: Not busy. r1: Busy. Do not write to register UAxD as long as BUSY is true. STPB w0: w1: ODD w0: w1: PAR w0: w1: Stop Bits One stop bit. Two stop bits. Odd Parity Even parity. Odd parity. Parity On No parity. Parity on. UAxCA 7 w 0 0 UART x Compare Address Register 6 5 4 3 2 1 0 Bit 7 to 0 of address 0 0 0 0 0 0 Res 164 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C UAxIM 7 w x - UART x Interrupt Mask Register 6 x - 5 x - 4 x - 3 x - 2 ADR 0 1 BRK 0 0 RCVD 0 Res ADR w0: w1: BRK w0: w1: RCVD w0: w1: Mask Compare Address Detected Disable interrupt. Enable interrupt. Mask Break Detected Disable interrupt. Enable interrupt. Mask Received a Telegram Disable interrupt. Enable interrupt. UAxIF 7 r Test - UART x Interrupt Flag Register 6 Test - 5 Test - 4 Test - 3 Test - 2 ADR x 1 BRK 0 0 RCVD 0 Res Test ADR r0: r1: BRK r0: r1: RCVD r0: r1: Reserved for test (do not use) Compare Address Detected No Interrupt. Interrupt pending. Break Detected No Interrupt. Interrupt pending. Received a Telegram No Interrupt. Interrupt pending. Micronas Feb. 10, 2005; 6251-579-1DS 165 CDC 32xxG-C DATA SHEET 166 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 26. I2C-Bus Master Interface The IC contains two independent I2C-bus master interface units (I2C), 0 and 1. These are pure master systems, multimaster busses are not realizable. The units contain read and write buffers with interrupt logic which makes automatic and software-independent operation possible for most types of I2C telegrams. Because of the internal clock pre-scaler, telegram clock rate does not depend on the system clock rate. Features - I2C master module - 5-byte transmit FIFO - 3-byte receive FIFO - Progammable input deglitcher WR_Data (subaddress=control info) D0 to D7 Address Decoder WR 0 Clock Prescaler half full empty control Write FIFO 5 x 11 1 f1 SR0.I2Cx in SR out Write Logic 2 SDAx SCLx busy I2CMx.DGL Read Logic Read FIFO 3x8 empty Ack = 0 received Deglitcher f1 SR D0 to D7 RD_Data DAT_ACK Q SR Q ADR_ACK Start Condition: - resets ACK flags - deletes Read FIFO Status Register I2C Interrupt Source D0 to D7 RD_Status Fig. 26-1: Block diagram of I2C-bus master interface Micronas Feb. 10, 2005; 6251-579-1DS 167 CDC 32xxG-C 26.1. Principle of Operation 26.1.1. General 26.1.2. Hardware Settings Since the telegram clock rate is register programmable there is no HW option for the I2C-Bus Master Interface. DATA SHEET value. By default, the input deglitcher is on, limiting the obtainable bit rate to 208.3 kbit/s (see Table 26-2). In standby mode the clock is halted. Programming of the I2C registers is possible and the Write-FIFO can be filled. Prior to operation, proper SW configuration of the U-Ports assigned to function as I2C Double Pull-down port has to be made. See table 26-1 and section "Ports" for details. The bit rate and the desired input deglitcher configuration has to be set up in register I2CMx in order to get into an active and useful mode. All other registers serve I2C data I/O purposes. 26.1.3. Initialization After system reset the I2C is in standby mode, i.e. the block internal clock is halted and all registers are set to their reset Table 26-1: Module-specific settings Module Name I2C0 HW Options Item U2.0 CAN0/SCL0 output multiplexer U2.1 CAN0/SDA0 output multiplexer I2C1 Address PM.U20 Initialization Item SCL0 SDA0 SCL1 SDA1 Setting U2.0 special out, double pull-down mode SR0.I2C0 U2.1 special out, double pull-down mode U5.1 special out, double pull-down mode SR0.I2C1 U5.2 special out, double pull-down mode data available in the Read-FIFO. - The `busy' flag I2CRSx.BUSY is activated by writing any byte to any one of the Write registers. It stays active until the I2C-bus activities are stopped after the stop condition generation. Moreover the ACK-bit is recorded separately on the bus lines for the address and the data fields. However, the interface itself can set the address ACK=0. In any case the two ACK flags show the actual bus condition. These flags will be reset with the next I2C start condition. There is one data acknowledge (DACK) flag available. It indicates the level of the last received ACK bit. It will be cleared to zero with the reception of a zero and it will be set to one with the reception of a one within the acknowledge field of a data byte. Thus, after the stop condition, it indicates whether the last of the data bytes was acknowledged or not. The bus activity starts immediately after the first write to the Write-FIFO. The transmission can be synchronized by an artificial extension of the low phase of the clock line. Transmission is not continued until the state of the clock line is high once again. Thus an I2C slave device can adjust the transmission rate to its own abilities. The figures 26-2, 26-3 and 26-4 show the basic principle of I2C telegram transmission as a quick reference. Refer to the official I2C documentation for more details. 26.1.4.1. Interrupt Generation and Operation The transmission of telegrams generates two classes of interrupts. - End-of-Telegram interrupt - Write-FIFO-Half-Full interrupt Enable Bit 26.1.4. Operation A complete telegram is assembled by the software out of individual sections. Each section contains 8-bit data. This data is written into one of the six possible write registers. Depending on the chosen address, a certain part of an I2C-bus cycle is generated: start, data, stop, with or without acknowledge. By means of corresponding calling sequences it is therefore possible to join even very long telegrams (e.g. long data files for auto increment addressing of I2C slaves). The software interface contains a 5-word-deep Write-FIFO for the control-data registers as well as a 3-word-deep ReadFIFO for the received data. Thus most of the I2C telegrams can be transmitted to the hardware without the software having to wait for empty space in the FIFO. All address and data fields appearing on the bus are constantly monitored and written into the Read-FIFO. The software can then check these data in comparison with the scheduled data. Every reception of a start or restart condition immediately empties the Read-FIFO. The Read-FIFO stops if it is full. It's not overwritten, further received data are lost. If a read instruction is handled, the interface must send the data word 0xFF so that the responding slave can insert its data. In this case the Read-FIFO contains the read-in data. If telegrams longer than 3 bytes (1 address, 2 data bytes) are received, the software must check the filling condition of the Write-FIFO and, if necessary, fill it up and read out the Read-FIFO. A variety of status flags is available for this purpose: - The `half full' flag I2CRSx.WFH is set if the Write-FIFO is filled with exactly three bytes. - The `empty' flag I2CRSx.RFE is set if there is no more 168 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 26.1.6. Precautions Switching off the I2C module by the corresponding enable flag in the standby register, and then re-enabling it, may result in the last transmitted byte being transmitted again. To avoid this situation, disable the corresponding port pin as special output during operation pausing. After re-enabling the module by setting the corresponding enable flag, wait at least the transmission time of one byte before re-enabling this special output. For the effect of CPU clock modes on the operation of this module refer to section "CPU and Clock System" (see Table 4-1 on page 41). Note: The I2C block uses U-Ports as connection to the outside world. This implies that neither logic output low level switching specs nor logic input value specs of the official I2C specification document are literally met. Refer to section "Ports" for the actual spec values of this implementation. The End-of-Telegram interrupt is generated if the Write-FIFO is empty and the stop condition is completed. The flag BUSY is zero in this case. A Write-FIFO-Half-Full interrupt is generated by the WriteFIFO each time the entry number reduces from 4 to 3 (`halffull' state, WFH flag set), but not before at least two entries have been transferred from the Write-FIFO to the SR. Reaching the fill level of 3 entries during re-filling the WriteFIFO may (but must not) generate an interrupt too. Those interrupts occurring during re-filling the Write-FIFO could be a source of problems. They would be served as soon as the momentary ISR is left. This situation would confuse the ISR seriously, because though the flag WFH is zero, the Write-FIFO is filled above the half-full level. The Write-FIFO-Half-Full interrupt is essential as start of a refill routine. This routine has to guarantee that at the end the fill state is definitely > 3 entries. In this way prepared, again dropping to 3 entries safely triggers the next Write-FIFOHalf-Full interrupt, starting the next refill routine. The strategy to obtain a fill state > 3, is to fill up to `half-full' state (WFH flag set), and then to add 2 entries above that. During this refill routine, all other interrupts have to be disabled. At the end of this refill routine, to avoid ambiguities, any I2C interrupt requests received in meantime, have to be cleared. 26.1.4.2. Example of Operation The software has to work in the following sequence (ACK=1) to read a 16-bit word from an I2C device address 0x10 (on condition that the bus is not active): -write 0x21 to -write 0xFF to -write 0xFF to -read RFE bit from -read dev. address from -read RFE bit from -read 1st databyte from -read RFE bit from -read 2nddatabyte from I2CWS0x I2CWD0x I2CWP1x I2CRSx I2CRDx I2CRSx I2CRDx I2CRSx I2CRDx 1T SDA SCL 1/2T 1T 1/4T Fig. 26-2: Start or restart condition I2C-bus 1T SDA repeated 8 times SCL 1/4T 1/2T 1/4T The value 0x21 in the first step results from the device address in the 7 MSBs and the R/W-bit (read=1) in the LSB. If the telegrams are longer, the software has to ensure that neither the Write-FIFO nor the Read-FIFO can overflow. To write data to this device: -write 0x20 to -write 1st databyte to -write 2nd databyte to I2CWS0x I2CWD0x I2CWP0x Fig. 26-3: Single bit on I2C-bus SDA SCL 1/4T 3/4T 26.1.5. Inactivation Since the described block is an I2C master, all I2C bus activity stops if the end of a telegram is reached. I2C slaves cannot start any bus activity on their own. However, the block internal clock is always running at full speed of I2C clock (4 or 5 MHz), independent of the bit rate divider setting. The standby mode is therefore intended for the lowest possible power consumption. Switching off the I2C module by the corresponding enable flag in the standby register may result in the output signal SDAx being drawn to zero for the time the I2C module is off. To avoid this situation, disable the corresponding port pin as special output during operation pausing and allow the port to return to high level. Fig. 26-4: Stop condition I2C-bus Micronas Feb. 10, 2005; 6251-579-1DS 169 CDC 32xxG-C 26.2. Registers DATA SHEET I2CWS0x 7 w I2C Write Start Register 0 6 5 4 3 2 1 0 Writing this register moves I2C Data, ACK=0 (acknowledge) and I2C stop condition into the Write FIFO. I2C Address 0x00 Res I2CRDx 7 r I2C Read Data Register 6 5 4 3 2 1 0 Writing this register moves I2C start condition, I2C Address and ACK=1 (no acknowledge) into the Write FIFO. I2C Data 0x00 Res Reading this register returns the content of the Read FIFO. I2CWS1x 7 w I2C Write Start Register 1 6 5 4 3 2 1 0 I2CRSx 7 Res r x 0 I2C Read Status Register 6 OACK 0 I2C Address 0x00 5 AACK 0 4 DACK 0 3 BUSY 0 2 WFH 0 1 RFE 0 0 x 0 Res Writing this register moves I2C start condition, I2C Address and ACK=0 (acknowledge) into the Write FIFO. OACK r: I2CWD0x 7 w "OR"ed Acknowledge AACK OR DACK. Address Acknowledge Not acknowledged (received a one) Acknowledged (received a zero) Data Acknowledge Not acknowledged (received a one) Acknowledged (received a zero) Busy I2C Master Interface is busy. I2C Master Interface is not busy. Write-FIFO Half Full Write-FIFO contains exactly 3 bytes. Write-FIFO contains more or less than 3 bytes. Read-FIFO Empty Read-FIFO is empty. Read-FIFO is not empty. I2C Write Data Register 0 6 5 4 3 2 1 0 AACK r1: r0: DACK r1: r0: BUSY r1: r0: WFH r1: r0: RFE r1: r0: I2C Data 0x00 Res Writing this register moves I2C Data and ACK=1 (no acknowledge) into the Write FIFO. I2CWD1x 7 w I2C Write Data Register 1 6 5 4 3 2 1 0 I2C Data 0x00 Res Writing this register moves I2C Data and ACK=0 (acknowledge) into the Write FIFO. I2CMx I2CWP0x 7 w I2C Mode Register 6 5 4 3 SPEED 0x02 Res I2C Write Stop Register 0 6 5 4 3 2 1 0 w 7 DGL 1 2 1 0 I2C Data 0x00 Res Writing this register moves I2C Data, ACK=1 (no acknowledge) and I2C stop condition into the Write FIFO. DGL Input Deglitcher w1: Deglitcher is active. w0: Deglitcher is bypassed. If the deglitcher is active, the maximum bit rate is limited. SPEED must be programmed to 6 at least. The maximum bit rate may be further reduced by the bus load. I2CWP1x 7 w I2C Write Stop Register 1 6 5 4 3 2 1 0 I2C Data 0x00 Res 170 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C SPEED w: Speed Select (Table 26-2) I2C Bit Rate = f1 / (4 x SPEED). Table 26-2: SPEED usage: I2C bit rates SPEED 0 1 1) 2 1) 3 1) 4 1) 5 1) 6 7 ... 127 127 x 4 f1 Division by 128 x 4 (!) 1x4 2x4 3x4 4x4 5x4 6x4 7x4 Bit Rate @ f1 = 5 MHz 9.8 kbit/s 1.25 Mbit/s 625 kbit/s 416.7 kbit/s 312.5 kbit/s 250 kbit/s 208.3 kbit/s 178.6 kbit/s ... 9.8 kbit/s 7.9 kbit/s Bit Rate @ f1 = 4 MHz 7.8 kbit/s 1.00 Mbit/s 500 kbit/s 333.3 kbit/s 250 kbit/s 200 kbit/s 166.7 kbit/s 142.9 kbit/s 1) These bit rates may only be set with a bypassed input deglitcher (I2CMx.DGL=0) Micronas Feb. 10, 2005; 6251-579-1DS 171 CDC 32xxG-C DATA SHEET 172 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 27. CAN Manual This manual describes the user interface of the CAN module. For further information about the CAN bus, please refer to the CAN specification 2.0B from Bosch. Features - Bus controller according to CAN licence specification 1992, 2.0B - Supports standard and extended telegrams - FullCAN: up to 32 Rx and Tx telegrams - Variable number of receive buffers - Programmable acceptance filter Single, group or all telegrams received. - Time stamp for each telegram - Overwrite mode programmable for each telegram - Programmable baud rate. Max. 1 MBd @ 8 MHz - Sleep mode The CAN interface is a VLSI module which enables coupling to a serial bus in compliance with CAN specification 2.0B. It controls the receiving and sending of telegrams, searches for Tx telegrams and interrupts and carries out acceptance filtering. It supports transmission of telegrams with standard (11bit) and extended (29-bit) addresses. The CAN interface can be configured as BasicCAN or FullCAN. It enables several active receive and transmit telegrams and supports the remote transmission request. The number of telegrams which can be handled depends mainly on the size of the communication RAM (16 byte per telegram), the system clock and the transmission speed. A maximum of 254 telegrams can be handled. A mask register makes it possible to receive different groups of telegram addresses with different receive telegrams. Transmitting or receiving of a telegram as well as the occurrence of an error can trigger an interrupt. CPU CAN Bus Address Error Management Logic Global Control and Status Register CAN RAM Data Interrupt Source (Com. Area) f0 Bit Timing Logic Protocol Manager Interface Management Logic Rx/TxBuffer Rx. Obj. Tx. Obj. Fig. 27-1: Block diagram of the CAN bus interface Micronas Feb. 10, 2005; 6251-579-1DS 173 CDC 32xxG-C 27.1. Abbreviations BI BTL CAN CA CO CM CRC DLC EoCA Ext. ID Ext. Tg GCS CAN Bus Interface Bit Timing Logic Controller Area Network Communication Area Communication Object Communication Mode Cyclic Redundancy Code Data Length Code End of CA Extended Identifier Extended Telegram Global Control and Status Register ID IML Rx. Obj. RxTg Std. ID Std. Tg TD Tg TQ Tx. Obj. TxTg Identifier Interface Management Logic Receive Object Receive Telegram Standard Identifier Standard Telegram Telegram Descriptor Telegram Time Quantum Transmit Object Transmit Telegram DATA SHEET 27.2. Functional Description 27.2.1. HW Description The CAN bus interface consists of the following components: Bit Timing Logic: Scans the bus and synchronizes the CAN bus controller to the bus signal. Protocol Manager: The PM monitors or generates the composition of a telegram and performs the arbitration, the CRC and the bit stuffing. It controls the data flow between Rx/Tx buffer and CAN bus. It also drives the error management logic. Error Management Logic: Adds up the error messages received from the protocol manager and generates error messages when particular values are exceeded. Guarantees the error limitation as per the CAN Spec. V2.0B. Interface Management Logic: The IML scans the Communication Area (CA) in the CAN-RAM for transmit telegrams. As soon as it finds one, it enters it into the Rx/Tx buffer and reports it to the protocol manager as ready for transmission. If a telegram is received, the IML carries out the acceptance filtering, i.e., scans the CA, taking into account the identifier mask register in the GCS, for a Tg with the appropriate address. After correct reception, it copies the Tg from the Rx/ Tx buffer to the CA. The IML also reports to the CPU the valid transfer of a telegram or given errors per interrupt. The interrupt source output of this module is routed to the interrupt controller logic. But this does not necessarily select it as input to the interrupt controller. Check section "interrupt controller" for the actually selectable sources and how to select them. Rx/Tx buffer: This is used to buffer a full telegram (ID, DLC, data) during sending and receiving. Global Control and Status Register: The GCS contains registers for the configuration of the BI. It also contains error and status flags and an identifier mask. The error counter and the capture timer can be read from the GCS. Receive Object: The BI enters received telegrams into a matching Rx-Object. It can be retrieved from the application. Transmit Object: The application enters data into the TxObject and reports it ready for transmission. The BI sends the telegram as soon as the bus traffic allows. For the effect of CPU clock modes on the operation of this module refer to section "CPU and Clock System" (see Table 4-1 on page 41). 27.2.2. Memory Map From the CAN bus interface the user sees two storage areas in the user RAM area. The BI is configured with the global control and status registers (GCS). It also indicates the status here. The communication area (CA) contains the Rx and Tx telegrams. The communication area lies in the CAN-RAM. The end of the communication area is fixed by the first control byte of an object whose 3 MSBs contain only ones (Communication Mode = 7 = EoCA). The area after this is available to the user. The CA consists of communication objects (COs). A CO consists of 6 bytes telegram descriptor (TD), 8 data bytes and the time stamp which is 2 bytes long. The TD contains the address (ID) and the length of a telegram (DLC) as well as control bits which are needed for access to the CO and for the transmission of a telegram. In the BasicCAN and the FullCAN versions, all the communication objects have the same, maximum size of 16 bytes. Unassigned storage locations in the data area of a CO can be freely used. The maximum number of COs is limited by the time which the CAN interface has to search for an identifier in the communication area. 174 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C timing, error status, output control registers, baud rate prescalers, Tx and Rx error counters as well as the capture timer. 27.2.3. Global Control and Status Registers (GCS) The GCS registers can be used to determine the behavior of the CAN interface. As well as flags for the interrupts, halt and sleep modes, they also contain interrupt index, ID mask, bus Global Control and Status Communication Area CTR STR ESTR IDX IDM BT1 BT2 BT3 ICR OCR TEC REC ESM CTIM 0 Control Status Error Status Interrupt Index ID Mask 28 ... 21 ID Mask 20 ... 13 ID Mask 12 ... 5 ID Mask 4 ... 0 Bit Timing 1 Bit Timing 2 Bit Timing 3 Input Control Output Control Transmit Error Counter Receive Error Counter 15 Error Status Mask 16 Capture Timer low 17 Capture Timer high 0 Control 1 ID 28 ... 21 2 ID 20 ...13 ID 12 ... 5 ID 4 ... 0 and Control DLC and Control Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Time Stamp low 15 Time Stamp high 16 TD Data and Time Stamp Com.-Obj. 1 Telegram Descriptor TD Com.-Obj. 2 31 32 TD Data and Time Stamp Com.-Obj. 3 47 n*16 TD Data and Time Stamp Com.-Obj. n n*16+15 (n+1)*16 Control: CM = 7 Fig. 27-2: Memory allocation Access modes: r: read w: write i: init (BI halted) w0: clear w1: set End of Com. Area halt acknowledge is indicated in the status register (HACK). Re-initialization can be carried out in the halt mode (HACK is set). After this, the halt flag must be deleted again. After a reset, HLT is set. If HLT is set during a Tx-Tg and this has to be repeated (error or no acknowledge), the BI stops yet. The corresponding TxCO is still reserved, however, and can no longer be operated from BI. Therefore, when HLT is set, the CA should always be re-initialized if the last Tx-Tg has not been correctly transmitted (Status Transfer Flag is still deleted). If HLT is set during the BI is in Bus-Off mode, the BI stops after Bus-Off mode is finished. Flag BOFF is cleared then and receive and transmit error counters are reset to zero. SLP Sleep r/w0: Run. r/w1: Sleep. The BI goes into the sleep mode when the sleep flag is set and a started Tg is terminated. The sleep mode is finished as CANxCTR 7 r/w HLT 1 Control Register 6 5 GRSC 0 4 EIE 0 3 GRIE 0 2 GTIE 0 1 BOST 0 0 rsvd x Res SLP 0 HLT Halt r/w0: Run. r/w1: Halt. Switches the CAN interface into the halt mode. Transmissions which have been started are brought to an end. The Micronas Feb. 10, 2005; 6251-579-1DS 175 CDC 32xxG-C soon as a dominant bus level is detected, or the sleep flag is deleted. GRSC Global Rescan r0: Don't rescan. r1: Rescan w0: Unaffected w1: Set. The microprocessor can set this flag in order to initiate a transmit telegram search at the beginning of the communication area. The BI resets the bit. The BI also sets the GRSC flag if the flag RSC has been set in a telegram descriptor of a Tx-Tg just operated, and thereby initiates a rescan. If the microprocessor writes a zero, nothing happens. EIE r/w0: r/w1: GRIE r/w0: r/w1: GTIE r/w0: r/w1: Error-Interrupt-Enable Disabled. Enabled. Global Rx-Interrupt-Enable Disabled. Enabled. Global Tx-Interrupt-Enable Disabled. Enabled. DATA SHEET It is set even if an error counter is greater than 96. It means that a bit has been set in the error status register. As soon as all the flags in the error status register are either deleted or masked, ERS is also deleted. As long as a bit is set in the CANxESTR and not masked, the ERS bit is also set in the status register. If EIE has been set in the control register, an interrupt is triggered too; i.e., the value 254 is entered in the register CANxIDX as soon as it is free, and the interrupt source output is triggered. To erase a bit in the CANxESTR the user must write a one at the appropriate place. Places at which he writes a zero will not be changed. Because it makes sense to erase only those bits which have previously been read, only the value which has been read has to be re-written. CANxESTR 7 r/w GDM 0 Error Status Register 5 ECNT 0 6 CTOV 0 4 BIT 0 3 STF 0 2 CRC 0 1 FRM 0 0 ACK 0 Res BOST Bus-Off Stop Select r/w0: Don't stop when leaving Bus-Off mode. r/w1: Stop when leaving Bus-Off mode. The flag HLT is set by the BI after leaving the Bus-Off recovery sequence. The SW has to restart the CAN module in this case after re-initialisation. Consider the flag HACK even in this case. Read-modify-write operations on single flags of this register must be avoided. Unwanted clearing of other flags of this register may be the result otherwise. GDM Good Morning r0: No wake-up. r1: Wake-up. w0: Unaffected. w1: Clear. Is set by the BI when it is aroused from the sleep mode by a dominant bus level. The user must delete it. CTOV Capture Time Overflow r0: No overflow. r1: Overflow. w0: Unaffected. w1: Clear. Is set by the BI when the capture timer (CTIM) overflows. The user must delete it. ECNT Error Counter Level r0: No error counter. r1: Error counter. w0: Unaffected. w1: Clear. Is set by the BI as soon as the transmit error counter or the receive error counter exceeds a limit value. The user must delete it. BIT Bit Error r0: No bit error. r1: Bit error. w0: Unaffected. w1: Clear. Is set by the BI when a transmitted bit is not the same as the bit received. The user must delete the flag. STF Stuff Error r0: No stuff error. r1: Stuff error. w0: Unaffected. w1: Clear. Is set by the BI when 6 identical bits are received successively in one Tg. The user must delete it. CRC r0: CRC Error No CRC error. CANxSTR 7 r HACK 1 Status Register 6 5 EPAS 0 4 ERS 0 3 rsvd x 2 rsvd x 1 rsvd x 0 rsvd x Res BOFF 0 HACK Halt-Acknowledge r0: Running. r1: Halted. Is set by the BI when it enters the halt mode. It is deleted again when the halt mode is exited. BOFF Bus-Off r0: Bus active. r1: Bus off. With this flag the BI indicates whether the node is still actively participating in the bus. If the transmit error counter reaches a value of > 255 (overflow), the node is separated from the bus and the flag is set. The bus-off mode is left after the bus-off recovery sequence. The flag CANxCTR.BOST defines the behavior after leaving bus-off mode. EPAS Error-Passive r0: Error active. r1: Error passive. With this flag the BI indicates whether the node is still participating in the bus with active error frames. If an error counter has reached a value > 127, the node only transmits passive error frames and the flag is set. ERS Error-Status r0: No Errors. r1: Errors. This flag is set when the BI detects an error and the appropriate error flag is not masked in the error status mask register. 176 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C r1: CRC error. w0: Unaffected. w1: Clear. Is set by the BI when the CRC received does not coincide with the CRC calculated. The user must delete it. FRM Form Error r0: No form error. r1: Form error. w0: Unaffected. w1: Clear. Is set by the BI when an incorrect bit is received in a field with specified bit level (start of frame, end of frame, ...). The user must delete it. ACK Acknowledge Error r0: No acknowledge error. r1: Acknowledge error. w0: Unaffected. w1: Clear. Is set by the BI when there is no acknowledge for a transmitted Tg. The user must delete it. CANxBT1 7 r/w MSAM 0 Bit Timing Register 1 6 5 4 3 BPR 0 0 0 0 0 0 Res 2 1 0 SYN 0 MSAM r/w0: r/w1: SYN r/w0: r/w1: Multi Sample Bus level is determined only once per bit. Bus level is determined three times per bit. Sync On Synchronization with falling edges only. Synchronization with rising edges too. BPR Baud Rate Pre-scaler r/w: Prescaler value. The baud rate prescaler sets the length of a time quantum for the bit timing logic. tQ = (BPR + 1) / f0. With the 6-bit counter it is possible to extend tQ by a factor of 1...64. Values from 0 to 63 are allowed. CANxIDX 7 r/w 1 1 Interrupt Index Register 6 5 4 3 2 1 0 Interrupt Index 1 1 1 1 1 1 Res 0: tQ = 1 / f0 1: tQ = 2 / f0 2: tQ = 3 / f0 3: tQ = 4 / f0 etc. The interrupt index indicates the source of the interrupt. If a transmission was the cause of an interrupt, the interrupt index points to the corresponding telegram descriptor (CANxIDX = 0..253). If an error was responsible for the interrupt, the interrupt index designates the error status register (CANxIDX = 254). After dealing with the interrupt, the user must eliminate the cause of the interrupt and set the interrupt index to minus one (255 = EMPTY). As soon as CANxIDX is empty, the BI can enter a new index and initiate an interrupt. An interrupt can only be initiated when CANxIDX contains the value 255. CANxBT2 7 r/w rsvd 0 0 Bit Timing Register 2 6 5 TSEG2 0 0 0 0 4 3 2 TSEG1 1 0 0 0 Res TSEG2 Time Segment 2 r/i: TSEG2 value. TSEG2 determines the number of time quanta after the sample point. Permitted entries: 1...7 (result in 2...8 TQ). TSEG1 Time Segment 1 r/i: TSEG1 value. TSEG1 determines the number of time quanta before the sample point. Permitted entries: 2...15 (result in 3...16 TQ). CANxIDM 7 r/w r/w r/w r/w 0 0 Identifier Mask Register 6 5 4 3 2 x 1 x 0 x 3 2 1 0 Identifier Mask Bits 4 to 0 Identifier Mask Bits 12 to 5 Identifier Mask Bits 20 to 13 Identifier Mask Bits 28 to 21 0 0 0 0 0 0 CANxBT3 7 r/w rsvd x Bit Timing Register 3 6 5 rsvd x 4 rsvd x 3 rsvd x 2 1 SJW 0 rsvd x Res 0 0 0 Res r/w0: Don't care. r/w1: Compare. The identifier mask register is 29 bits long; the MSB is in the MSB position in the lowest byte address. The CANxIDM defines a mask for the acceptance of address groups. Only the permitted bits are used for comparison with a received identifier. Whether the mask is used can be determined individually for each receive object. SJW Synchronization Jump Width r/i: SJW value. SJW defines by how many TQs a bit may be lengthened or shortened because of resynchronization. Permitted entries: 1...4 (result in 1...4 TQ). Only the values 1, 2, 3 and 4 are allowed, other values result in unpredictable behavior. Micronas Feb. 10, 2005; 6251-579-1DS 177 CDC 32xxG-C ECTV r/w0: r/w1: 1 REF1 0 DATA SHEET CANxICR 7 r/w rsvd x Input Control Register 6 5 rsvd x Enable Capture Time Overflow Disable. Enable. Enable Error Counter Level Disable. Enable. Enable Bit Error Disable. Enable. Enable Stuff Error Disable. Enable. Enable CRC Error Disable. Enable. Enable Form Error Disable. Enable. Enable Acknowledge Error Disable. Enable. 4 rsvd x 3 rsvd x 2 XREF x 0 REF0 0 Res rsvd x EECT r/w0: r/w1: EBIT r/w0: r/w1: ESTF r/w0: r/w1: ECRC r/w0: r/w1: EFRM r/w0: r/w1: EACK r/w0: r/w1: XREF r/w0: r/w1: ity). REF1 r/w0: r/w1: REF0 r/w0: r/w1: External Reference (not avaliable) The internal reference is used. The external reference is used where available (write to zero for future compatibilUse Reference for RxD1 RxD is used as inverted input signal. Supply voltage is used as inverted input signal. Use Reference for RxD0 RxD is used as input signal. Ground is used as input signal. CANxOCR 7 r/w rsvd x Output Control Register 5 rsvd x 6 rsvd x 4 rsvd x 3 rsvd x 2 rsvd x 1 rsvd x 0 ITX 0 Res r CANxCTIM 7 6 Capture Timer 5 4 3 2 1 0 1 0 0 0 0 Res Timer Bit 15 to 8 Timer Bit 7 to 0 0 0 0 0 0 ITX r/w0: r/w1: Inverted transmission Tx output is not inverted. output is inverted. r CANxTEC 7 r 0 0 Transmit Error Counter 6 5 4 3 2 1 0 Counter Bit 7 to 0 0 0 0 0 0 0 Res The capture timer is incremented with a clock pulse derived from the CAN bus. Because it can only be read byte-wise, the low byte must be read first. The corresponding high byte is latched at the same time. When CANxCTIM overflows, the flag CTOV in the error status register is set. The capture timer will not be incremented during CAN module sleep mode (SLP = 1). CANxREC 7 r x x 0 Receive Error Counter 6 5 4 3 2 1 0 Counter Bit 6 to 0 0 0 0 0 0 0 Res CANxESM 7 r/w EGDM 1 Error Status Mask Register 5 EECT 1 6 ECTV 1 4 EBIT 1 3 ESTF 1 2 ECRC 1 1 EFRM 1 0 EACK 1 Res Every flag of the CANxESTR can be enabled/disabled generating an interrupt by modifying the corresponding flag in register CANxESM. EGDM r/w0: r/w1: Enable Good Morning Disable. Enable. 178 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C The COs are entered in order of priority into the CA. This starts with the highest priority (the lowest identifier). The identifier defines the priority of a telegram. If the first eleven bits of an extended telegram are the same as the identifier of a standard telegram, the telegram with the standard identifier has higher priority. 27.2.4.1. Telegram Descriptor (TD) The telegram descriptor is 6 bytes (TD0 to TD5) long and forms the beginning of a CO. Telegrams with standard and extended identifiers have different TDs. They differ only in the length of the identifiers. 18 bits therefore are not allocated in the TD of a standard telegram. They cannot be used by the application because they are overwritten by the reception of a telegram. 27.2.4. Communication Area (CA) The CA is located in the CAN-RAM. It consists of communication objects, each of which is 16 bytes long. The CA begins at address 0 of the CAN-RAM with the first byte of a CO. It ends with the first byte of a CO which contains ones in its 3 MSBs (communication mode = 7 = EoCA). The following bytes can be used by the application. If the CAN-RAM is filled completely with COs, there is no place left and no need to mark the end of CA. Every telegram which this node is to receive or transmit is represented by a CO. As well as the data and the time stamp, this also contains a header, the telegram descriptor (TD), in which the attributes of the communication object are stored. Extended Addr. Format (EXF is set) 0 1 28 2 20 3 12 44 5 ID DLC 7 6 5 4 3 2 1 0 Standard Addr. Format (EXF is deleted) rsvd LCK 21 13 5 0 1 28 2 20 3 4 5 don't use DLC TIE ID 18 don't use EXF RSR ACC RIE SR TS 7 6 5 4 3 2 1 0 CM RSC MID OW ID ID ID CM RSC MID OW ID don't use rsvd LCK 21 0 EXF RSR ACC TIE RIE SR TS Fig. 27-3: Extended and standard TD map Forms of access: r: read w: write i: init (BI halted or CM = inactive) w0: clear w1: set CM Communication Mode r/i: Mode. CM defines the type of telegram. 0: Inactive 1: Send 2: Receive 3: Fetch 4: Provide 5: Rx-All 6: rsvd 7: EoCA Inactive. No participation in the bus traffic. Send data. Receive data. Fetch data via remote frame. Have data fetched via remote frame. Receive every telegram. Don't use (provis. EoCA). End of Communication Area. If the rescan bit has been set in a transmit object just processed, the search for active Tx objects is started at the beginning of the communication area. Otherwise, the search continues at this transmit object until the end of the CA is reached. From there, the system jumps back to the beginning of the CA. MID Mask Identifier r/w0: Don't mask. r/w1: Mask. If MID is deleted, the identifier received is compared bit-bybit with the identifier from the telegram descriptor, i.e., the entire identifier must be the same so that the telegram received is transferred into this CO. If MID is set, only bits which are allowed in the ID mask register of the GCS are used for the comparison. OW Overwrite r/w0: Don't overwrite. r/w1: Overwrite. When OW is set, the com. object may be overwritten even if the application has not yet fetched the contents (TS set). The BI must of course obtain right of access (LCK deleted). LCK Lock r/w0: BI has right of access. r/w1: BI does not has right of access. Lock determines the right of access for the BI. As long as the CO is inactive (CM = 0) or locked (LCK = TRUE), the BI accesses the first byte of the CO only by reading. All other bytes are neither read nor written. The inactive mode is suitable therefore for re-configuration of a CO online; i.e., while the node is taking part in the bus traffic. RSC r/w0: r/w1: Rescan Don't rescan. Rescan. Micronas Feb. 10, 2005; 6251-579-1DS 179 CDC 32xxG-C ID Identifier r/i: Identifier. The ID contains the address of the telegram. 11 bits in the standard mode or 29 bits in the extended mode. ACC Access r/w0: CPU does not have right of access. r/w1: CPU has right of access. Access determines the right of access for the CPU. The CPU should not modify this flag after initialization. In operation mode only the BI modifies it and the CPU reads it. RSR Remote Send Request r/w0: Remote telegram received. r/w1: Corresponding data transmitted. In the provide mode, RSR signals a send request from outside; in the fetch mode it means that a remote telegram is being sent. It is set by the BI if a remote telegram has been received. It is deleted as soon as the corresponding data telegram has been transmitted. EXF Extended Format r/w0: Standard. r/w1: Extended. In order to send/receive telegrams with extended address format, this flag must be switched on. For standard telegrams it is deleted. DLC Data Length Code r/w: Data length. The DLC defines the number of data bytes transmitted. Only telegrams with 0 to max. 8 data bytes are transmitted. If the DLC of a TxTg contains a value >8, the entered DLC and exactly 8 bytes will be transmitted. In the case of RxTgs the received DLC, and therefore also values > 8 will be entered by BI. TIE Tx Interrupt Enable r/w0: Disable. r/w1: Enable. Masks the Tx interrupt for this com. object. RIE Rx Interrupt Enable r/w0: Disable. r/w1: Enable. Masks the Rx interrupt for this communication object. DATA SHEET SR Send Request r0: Successful transmission. r/w1: Send request. With SR, the microprocessor issues a send request. Both the microprocessor and the BI write the SR flag. If the microprocessor writes a one, the telegram is sent. The BI deletes the SR flag after successful transmission. TS Transfer Status r/w0: Ready for Transfer. r/w1: Successful transfer. The TS flag is set by BI after a successful transfer and is deleted by the microprocessor after a com. object has been processed. 27.2.4.2. Data Field The data field consists of 8 Byte. They are filled with telegram data according to the DLC. Unused data bytes (DLC less than 8) can be used by the user. 27.2.4.3. Time Stamp TIMST Time Stamp r: Counter value. The last two bytes in the CO are used for the time stamp. At each SoF (Start of Frame) the free-running 16-bit counter CANxCTIM is loaded into a register. When the telegram has been correctly transmitted, this register is copied to the two time stamp bytes of the corresponding CO. Data 5 Data 6 Data 7 14 Time Stamp low 15 Time Stamp high Fig. 27-4: Time stamp 27.3. Application Notes 27.3.1. Initialization After reset, a CAN Module is in standby mode (inactive). Prior to entering active mode, proper SW configuration of the U-Ports assigned to function as RX input and TX output has to be made (Table 27-1). The RX port has to be configured as special in and the TX port has to be configured as special out. Refer to "Ports" for details. For entering active mode of a CAN, set the respective enable bit (Table 27-1). In the initialization phase, a configuration of the CAN node takes place. The mode of operation of the BTL and the bus coupling is set. The communication area is created in the CAN-RAM. The different telegrams are specified in it. The CAN node must be halted (HACK = TRUE) to carry out the initialization. After a reset, the flags HLT and HACK are set and initialization can take place. If initialization is required on-line, the flag HLT must be set. However, the BI must terminate any current transmission before it comes to a halt. For the user this means that he must wait until HACK has been set. If HLT is deleted after initialization, then BI begins to participate in the bus traffic and to scan the CA for tasks. During initialization, the error status register (CANxESTR) and the interrupt index (CANxIDX) should be deleted, otherwise no interrupts can be initiated. The error status mask register default value after reset is not masked. If telegrams with different identifiers are to be received in a single CO, the identifier mask register must be initialized. This defines which bit of the ID received must be the same as the ID in the CO. Bit timing registers 1, 2 and 3 and the output control registers 1 and 2 must be initialized in all cases. 180 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Table 27-1: Module-specific settings Module Name CAN0 HW Options Item CAN0-RX input multiplexer CAN0-TX output multiplexer CAN1 Initialization Address Item PM.U20 CAN0-RX CAN0-TX CAN1-RX CAN1-TX CAN2 CAN2-RX CAN2-TX CAN3 CAN3-RX CAN3-TX The CA must be created in the CAN-RAM. The different COs are created one after the other starting at the address 0. It is important at this point that the three MSBs have been set in the first byte after the last CO, i.e., at an address divisible by 16 (CM = End of CA). This is not necessary if the CAN-RAM is completely filled with COs. Communication mode (CM), identifier, data length code, extended format flag (EXF) and remote send request flag must be initialized in each CO. Lock flag (LCK) must be deleted and access flag (ACC) must be set in order that the BI may also view this CO. Transfer status flag (TS) must be deleted so that interrupts are not initiated erroneously. Setting U2.1 or U4.3 special in U2.0 or U4.2 special out U6.1 special in U6.0 special out U8.5 special in U8.4 special out U8.3 special in U8.2 special out SR0.CAN3 SR0.CAN2 SR0.CAN1 SR0.CAN0 Enable Bit When the BI is accessing a com. object, it first deletes ACC and then reads LCK. If LCK is FALSE, it has right of access. ACC = FALSE; if (LCK == FALSE) { /* BI has right of access */ } ACC = TRUE; Fig. 27-6: Access to a CO by the BI The BI does not wait at a CO until it becomes free. 27.3.2. Handling the COs 27.3.2.1. Principles If the user wishes to access a CO, then he must lock out the BI from access to it. Also the BI reserves access for itself to one CO. In this case the user may not have access. When scanning the CA, the BI ignores inactive or locked COs; i.e., it reads only the first byte and then jumps to the next CO. Reservations Procedure If the user would like to access a com. object, then he must first set LCK. Then he must read ACC. If it is TRUE, he has right of access. After the operation he must delete LCK. The BI scans the CA from beginning to end. After a TxTg has been transmitted, the next TxTg entered is reported ready to send. It makes sense to enter the COs in the CA in order of their priority. The priority is determined by the ID. The lowest ID has the highest priority. If the first bits of an extended ID are identical with a standard ID, the standard ID has higher priority. The CO with the highest priority is at the beginning of the CA. This ensures that Tx-Tgs with high priority are transmitted first when a rescan is initiated. 27.3.2.2. Configuration A CO may be configured only in the inactive and/or locked mode or when HACK has been set. Otherwise it can lead to access conflicts between the user and BI. The communication mode (CM) is determined in the configuration phase. The identifiers are also entered. The flag EXF must not be overlooked. The flag RSR and DLC determine whether and how many data bytes will be transmitted in the telegram. The interrupts can be permitted. In case of a receive telegram it is necessary under certain circumstances to set the flags MID and OW. In case of a transmit telegram, the flag RSC must be adjusted. LCK = TRUE; if (ACC == TRUE) { /* CPU has right of access */ } LCK = FALSE; _______________ or _________________ LCK = TRUE; while (ACC == FALSE) { /* wait until BI is ready */ } /* CPU has right of access */ LCK = FALSE; Fig. 27-5: Access to a CO by the user Micronas Feb. 10, 2005; 6251-579-1DS 181 CDC 32xxG-C 27.3.2.3. Transmit Telegram CM = Send A transmit telegram is used to send data. How many data bytes will be sent is fixed in the DLC. The data is entered directly after the TD. Unused data bytes can be freely used by the user. If after the transmission of this telegram the user would like the next Tx-Tg in the CA to be sent, he deletes the RSC flag. If he sets the RSC, then the transmit search starts again at the beginning of the CA. The RSR flag has to be deleted. The set SR flag tells BI that this telegram is to be sent; SR can be likened to a postage stamp. The TS flag must be deleted before the CO is released with the deletion of LCK. If the BI finds a CO whose SR flag has been set, it reserves this (ACC = FALSE) and reports it "ready to send". It will be transmitted as soon as no higher-priority telegrams occupy the bus. After successful transmission, it deletes the flag SR and sets TS. The setting of ACC re-releases the CO. Whether an interrupt will be triggered depends on whether CANxIDX in the GCS contains the value minus one (255) and transmit interrupts are permitted. The user should now reserve the CO, reset the flag TS and delete CANxIDX so that other interrupts can also be reported. Should he wish to send further data, he can now enter this. 27.3.2.4. Receive Telegram CM = Receive With a receive telegram, data is received. If the EXF flag and the unmasked bits of the identifier of a received telegram are the same as those of a receive CO, the telegram will be copied to the CO. ID, DLC and data bytes are overwritten by the received ID, DLC and data. Only as many data bytes as the received DLC specify will be overwritten (max. 8). The DLC actually received will be entered. A permitted receive CO is only used when TS has been deleted or OW has been set. Once a telegram has been received and copied to a CO, the flag TS is set. An interrupt will also be initiated if receive interrupts are permitted and CANxIDX contains the value minus one (255). If the user detects the reception of a telegram (TS set), he must reserve the CO. Then he can read the data and, before releasing the CO again, delete TS. 27.3.2.5. Receive All Telegrams CM = Rx-All If, while searching for an RX-CO, the BI comes across a free Rx-All-CO, the received telegram will be entered here without regard to ID and EXF. Rx-All-COs should be applied at the end of the CA. 27.3.2.6. Fetch Telegram DATA SHEET this Tg. No data is therefore sent with it. If another node has the desired data available, this is transmitted with the same ID as soon as bus traffic allows. In this mode, only the reception of the data telegram can trigger an interrupt. The sequence of a fetch cycle is represented for the user in pseudo-code. if (TS == FALSE && SR == FALSE) /* CO is empty */ { LCK = TRUE; /* claim CO */ /* wait until BI released this CO */ while (ACC == FALSE) {/* do anything else */} SR = TRUE; /* send this Tg */ TS = FALSE; LCK = FALSE; /* release CO */ } The BI now transmits the telegram with the RTR flag set. The other node receives the Tg, provides the data and returns the telegram with RTR flag deleted. After the reply telegram has been received, the BI sets the flag TS. The user waits for the data. /* wait for answer */ while (TS == FALSE) {/* do anything else */} LCK = TRUE; /* claim CO */ /* wait until BI released this CO */ while (ACC == FALSE) {/* do anything else */} /* copy data */ TS = FALSE; LCK = FALSE; /* release CO */ Instead of waiting for the answer, it is also possible for notification to be given by a receive interrupt. 27.3.2.7. Provide Telegram CM = Provide A provide CO is used to prepare data for fetching. It is the counterpart of a fetch CO. In a provide CO the RSR flag is cleared. It will be set and deleted by the BI. The data can be prepared in two ways: In the first case, the user does not become active until a remote frame has been received (Rx interrupt or polling from RSR). After the CO has then been reserved, the data is written, the SR flag is set and the CO is released. The BI ensures then that the data is transferred back. In the second case, the data has already been entered, SR has been set and TS deleted before the request. When the remote frame is received, the user does not need to become active. Also, no Rx interrupt will be initiated. The data is simply fetched. In this case the requesting RTR telegram must contain the correct DLC because, with an RTR telegram too, a received DLC overwrites the local DLC. In both cases a Tx interrupt can occur after the data telegram has been transmitted. 27.3.2.8. Data Length Code The data length code is 4 bits long. It can therefore contain values between 0 and 15. In principle, no more than 8 bytes can be transmitted. Empty data telegrams (DLC = 0) are also possible. CM = Fetch A fetch CO is used to request data from another node. This is done by sending a telegram with the identifier of the desired data. The remote transmission request flag is set in 182 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C It is also possible to configure a rescan strategy statically. Each Tx-CO has the rescan flag RSC. If it is set, the system starts from the beginning with the transmit search after this CO has been processed. It is possible, for instance, to set RSC in the low-priority Tx-COs. Each time a low-priority TxCO has been handled, the search continues for higher-priority objects. The user must ensure that each Tx-CO is processed. If a telegram with a DLC greater than 8 is received, this value will be written into the DLC of the CO, but exactly 8 bytes of data will be copied. If the DLC of a Tx-CO contains a value greater than 8, this DLC will be transmitted, but only 8 bytes of data. 27.3.2.9. Overwrite Mode The BI normally processes a CO only when the transfer status TS has been deleted; i.e. the user has processed the CO since the last transmission. In the case of COs with which telegrams are received, the TS flag can be by-passed. If overwrite (OW) is permitted, the BI may overwrite a previously received telegram. When accessing data therefore, the user always receives the most up-to-date data. 27.3.5. Time Stamp The time stamp of a CO shows the user how much time has elapsed since the transmission of the object. For this purpose, he compares the time stamp with the capture timer CANxCTIM. Because the time stamp contains the value of the CANxCTIM at the time of the start of transmission, the difference is proportional to the time which has elapsed. The time stamp mechanism also enables network-wide synchronization. A master transmits a Tg. All nodes note the transmission time (local time). Then the master transmits its own (global) transmission time. The difference between local and global time shows by how much one's own clock (timer) is wrong. 27.3.3. Interrupts All interrupts are enabled or disabled by the global interrupt enable flags, GTIE for Tx interrupts, GRIE for Rx interrupts and EIE for error interrupts in the CANxCTR register. Each error interrupt can also be masked individually in the Error Status Mask register. A Tx interrupt can be enabled in the corresponding CO with the Tx interrupt enable flag TIE. An Rx interrupt can be enabled in the corresponding CO with the Rx interrupt enable flag RIE. An interrupt can only be initiated when the interrupt index CANxIDX is empty (minus one). To initiate an interrupt, the BI enters the number (0...253) of the appropriate CO in the CANxIDX. When an error interrupt is involved, the number 254 is entered. The BI attempts to initiate an interrupt immediately after successful transfer. If this does not work (CANxIDX not empty), the interrupt is pending (also error interrupt). The BI permanently scans the CA. If, while doing so, it finds a CO whose interrupt condition is satisfied (e.g. TIE and TS are set), it generates an interrupt. This means that interrupts not yet reported will not be reported in the sequence of their occurrence, but in the sequence in which they are discovered later. The interrupt service routine of the user must read the CANxIDX. The interrupt source is stored here. If CANxIDX points to a CO (0...253), the user must reserve this. After this, he must first delete TS so that this CO does not initiate an interrupt again. Only then he may release CANxIDX (CANxIDX = 255) so that the BI can enter further interrupts. 27.3.6. Errors In the error status register (CANxESTR) error messages and status data are collected which can generate an error interrupt. As long as a flag is set in the CANxESTR and not masked in the CANxESM, the flag ERS is also set in the status register. This means that the value 254 is written in CANxIDX and an interrupt is generated when EIE has been set. An error interrupt is deleted by first deleting CANxESTR and then releasing CANxIDX. The 5 flags BIT, STF, CRC, FRM and ACK originate from the protocol manager. The flag GDM (Good Morning) is not an error flag. GDM is set when the BI is aroused from the sleep mode by a dominant bus level. The flag ECNT (error counter level) indicates that an error counter has exceeded a limit value. It is set when the transmit error counter exceeds the values 95, 127 and 255 or the receive error counter exceeds the values 95 and 127. When the BI is in the Bus-Off mode, it no longer actively participates in the bus traffic. Nor does it receive telegrams, but continues to observe the bus. As soon as the BI has detected 128 x 11 successive recessive bits, it either reverts to the error-active mode if flag BOST is zero, or it sets the flag HLT and enters the HALT mode if flag BOST is set. At the same time the error counters are cleared. A Bus-Off sequence triggers two interrupts, if the error interrupt is enabled. The first interrupt (ECNT=TRUE) indicates that the transmit error counter has exceeded the value 255. This means that the module is in the Bus-Off mode now (BOFF=TRUE). The receive error counter is used to count the reception of 128 x 11 successive recessive bits in the Bus-Off mode. This is the reason for the second interrupt (ECNT=TRUE), which indicates that the receive error counter has exceeded the value 95 (warning level). The second interrupt can be ignored in Bus-Off mode. The error interrupt can be disabled during Bus-Off mode to avoid this second interrupt. 27.3.4. Rescan The normal transmit strategy searches for the next transmit CO in the CA. If all the transmit COs are ready to send, they are processed one after the other. This is a democratic strategy. If higher-priority TxTgs are reported in the meantime, these are not processed until the complete list has been finished. With rescan, the search for Tx telegrams is started again at the beginning of the CA. By this means the user can force the normal strategy to be interrupted and a search to be made first of all for higher-priority TxTgs. A transmit CO already reported will of course be transmitted first. The rescan requirement can be achieved dynamically, when a transmit CO is reported, by setting the global rescan flag GRSC. Micronas Feb. 10, 2005; 6251-579-1DS 183 CDC 32xxG-C 27.3.7. Layout of the CA The CA contains all COs beginning with the lowest identifier. The three MSBs must be set in the byte after the last CO (End of CA). If the BI has received an identifier complete, it starts at the beginning of the CA with the search for an appropriate RxCO. If a rescan is initiated, the BI also starts from the beginning with the transmit search. 27.3.7.1. Buffers Several successive receive COs may be allocated with the same identifier. The BI stores a received Tg in the first free Rx-CO. Using this mechanism it is possible to construct a receive buffer. If RIE is set in the last CO, the CPU is not informed until the buffer is full. 27.3.7.2. Basic/Full CAN For a Basic CAN application, a single Tx-CO will be used. All outgoing telegrams will be transmitted with this. The user must receive all Rx-Tgs and must himself decide whether he needs it (acceptance filtering). For this case it is possible to use an Rx-All-CO. But it is necessary to ensure that this can be processed before the next Tg arrives. For this reason, it is a good idea to employ 2 or 3 Rx-All-COs as buffers after the Tx-CO. In the case of a FullCAN application, the built-in acceptance filtering can be used and a dedicated CO can be set up for each desired Rx-Tg and Tx-Tg. If the CAN-RAM is not big enough, mixed strategies are also possible. The acceptance filtering, of course, burdens the CPU with communication tasks. Tx-Obj TD: CM= Receive Rx-Obj DATA SHEET TD: CM=Send Tx-Obj TD: CM=Send TD: CM= Receive Rx-Obj TD: CM= Rec. All Rx-Obj TD: CM= Rec. All Rx-Obj TD:CM = 7 End of Com. Area Fig. 27-8: Example: CA of a FullCAN with 2 Rx-objects, TD: CM=Send Tx-Obj 2 Tx-objects, and 2 Rx-buffers TD: CM= Rec. All Rx-Obj TD: CM= Rec. All Rx-Obj TD:CM = 7 End of Com. Area Fig. 27-7: Example: CA of a BasicCAN with 2 Rx-buffers 184 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C TD: CM=Send Tx-Obj CAN RAM Size Max. Number CO = ---------------------------------------16 - The next limiting factor can be calculated from the baud rate and system clock. After the BI has received an identifier, it must be possible for it to scan the entire CA before the telegram comes to an end. TD: CM= Rec. All Rx-Obj TD: CM= Rec. All Rx-Obj tCA SCAN Max. Number CO = ---------------------t CO SCAN t CO SCAN = 9 ---f0 t CA SCAN = 28 t Bit TD: CM= Rec. All Rx-Obj t Bit = ( 3 + TSEG1 + TSEG2 ) t Q t Q = BPR + 1 ------------------f0 TD: CM= Rec. All Rx-Obj tCA Scan is the time from having received an ID to the end of a minimum telegram (11-bit ID, no data), which is at the BI's disposal to scan the CA. tCO Scan is the worst case time needed by the BI to process an object (A value of 6 I/O cycles is a more realistic size than 9). With an input frequency of 8 MHz and a baud rate (1/tbit) of 1 MBd, the BI could handle 24 COs. Naturally, this value needs to be rounded off. - The value thus calculated is further limited, however, by the CPU accesses to the CAN-RAM. Each I/O cycle required by the CPU to write or read data in the CANRAM is missing from the BI. The BI is halted by CPU accesses. This reduces the time which the BI has to scan the CA. Where there is a reduced CPU clock, in particular, the user should have only limited access to the CANRAM. With the ARM CPU accessing CAN RAM, it is easy to block the BI's CAN-RAM access over a long time. The ARM CPU can make a memory access with each I/O cycle, leaving nearly no I/O cycles to the BI. In the above example (8 MHz, 1 MBd), tCA Scan lasts 224 I/O cycles (28 x 8). The BI needs 144 I/O cycles to scan 16 COs leaving 80 I/O cycles to the CPU to process a telegram. It is not necessary to process more than one telegram during transmission of one telegram. As long as the COs are managed via interrupt, 80 I/O cycles should be more than enough to read or write a CO. In this worst case scenario the BI needs 288 I/O cycles to scan 32 COs. This is possible at an input frequency of 8 MHz and up to baud rate of 500 kBd. In a more realistic estimation (average tCO Scan = 6) the BI needs 192 I/O cycles to scan 32 COs leaving 32 I/O cycles to the CPU to process a telegram. This means 1 MBd is possible even with 32 COs, as long as the COs are managed via interrupt only. Due to this, care has to be taken when using free CANRAM (after EoCA). It is not possible here, to make an assumption about how many accesses a non-CAN routine makes to its data storage. TD:CM = 7 End of Com. Area Fig. 27-9: Example: CA of a basicCAN with 4 Rx-buffers 27.3.7.3. Bus Monitor With some Rx-All-COs it is possible to construct a userfriendly bus monitor. The CPU merely has to observe whether anything has been received. The contents of the CO must be stored. The transmission time can be calculated from the time stamp. 27.3.7.4. Maximum number of COs The maximum number of COs depends on the size of the CAN-RAM, the baud rate, the system clock, the BI and the CPU accesses to the CAN-RAM. - The BI can handle a maximum of 254 objects. The limiting factor is the 8-bit register CANxIDX in the GCS. CANxIDX can contain 256 different values. The values 255 (empty) and 254 (error) are reserved. The remaining values 0...253 can indicate 254 objects. - The maximum number of COs is, of course, limited to a greater extent by the size of the CAN-RAM. The BI can only access the CAN-RAM. Therefore the CA can only be applied there. 16 bytes are reserved for each CO. One extra byte for coding EoCA after the last CO must not be forgotten. The CAN-RAM area after the EoCA is freely available to the user. No EoCA is necessary if the CAN-RAM is filled completely with COs. A maximum number of 32 COs is possible in a CAN-RAM of 512 bytes. Micronas Feb. 10, 2005; 6251-579-1DS 185 CDC 32xxG-C 27.4. Bit Timing Logic In the bit timing logic the transmission speed (baud rate) and the sample point within one bit will be configured. By shifting the sample point it is possible to take account of the signal propagation delay in different buses. Furthermore, the nature of the sampling and the bit synchronization can also be defined. DATA SHEET Phase Seg. Phase segments 1 and 2 are necessary to compensate phase differences. They can be lengthened or shortened by resynchronization. Sample Point The bus level is read at this point and interpreted as a received bit. TSEG1 The CAN implementation combines propagation delay segment and phase segment 1 to form time segment TSEG1. TSEG2 TSEG2 corresponds to phase segment 2. SJW The synchronization jump width gives the maximum number of time quanta by which a bit may be lengthened or shortened by resynchronization. 27.4.1. Baud Rate Pre-scaler The baud rate pre-scaler is a 6-bit counter. It divides the system clock down by the factor 1...64. The output is the clock for the bit timing logic. This clock TQCLK defines the time quantum (tQ). The time quantum is the smallest time unit into which a bit is subdivided. 27.4.2. Bit Timing A bit duration consists of a programmable number of TQCLK cycles. The cycles are split up into the segments SYNCSEG, TSEG1 and TSEG2. 27.4.2.1. Bit Timing Definition Sync.Seg. It is expected that a bit will begin in the synchronization segment. If the bit level changes, the resynchronization ensures that the edge lies inside this segment. The sync.seg is always one time quantum long. Prop.Seg. This part of a bit is necessary to compensate for delay times of the network. It is twice the sum of the signal propagation delay on the bus plus input comparator delay plus output driver delay. t Bit = t SYNCSEG + t TSEG1 + t TSEG2 t Q = BPR + 1 ------------------f0 t SYNCSEG = 1 t Q t TSEG1 = ( TSEG1 + 1 ) t Q t TSEG2 = ( TSEG2 + 1 ) t Q t SJW = SJW t Q tBit 1 time quant sample point Sync Seg tSYNCSEG Prop Seg tTSEG1 Phase Seg1 Phase Seg2 tTSEG2 def. CAN-SPEC impl. CAN Fig. 27-10: Bit timing definition The baud rate is then calculated as follows: 27.4.2.2. Bit Timing Configuration Certain boundary conditions need to be observed when programming the bit timing registers. The correct location of the sample point is especially important with maximum bus length and at high baud rate. 1BR = ------t Bit ( BPR + 1 ) ( 3 + TSEG1 + TSEG2 ) t Bit = ---------------------------------------------------------------------------------------f0 f0 BR = ---------------------------------------------------------------------------------------( BPR + 1 ) ( 3 + TSEG1 + TSEG2 ) 186 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C not necessary. If SYN is set, synchronization will also be made with the soft edge (dominant to recessive) and this will mean higher demands being imposed on the clock tolerances. 27.4.2.3. Synchronization The BTL carries out synchronization at an edge (change of the bus level) in order to compensate for phase shifts between the oscillators of the different CAN nodes. 27.4.2.4. Hard Synchronization t TSEG2 2 t Q t TSEG2 t SJW t TSEG1 3 t Q t TSEG1 t TSEG2 t TSEG1 t PROP + t SJW = Information Processing Time The information processing time is the internal processing time. After reception of a bit (sample point) this time is needed to calculate the next bit for transmission. With a baud rate of 1 MBd a bit should be at least 8 tQ long. In the case of a triple sample mode (MSAM = 1), the following boundary condition must also be observed: Hard synchronization is carried out at the start of a telegram. The BTL ensures that the first negative edge is in the sync. seg. 27.4.2.5. Resynchronization Resynchronization takes place during the transmission of a telegram. If the BTL detects an edge outside the sync. seg., it can lengthen or shorten the bit. If it detects the edge during TSEG1, tTSEG1 is lengthened. If it detects the edge during TSEG2, tTSEG2 is shortened. In this way, it ensures that the edges lie in the sync. seg. TSJW is the maximum time a bit can be lengthened or shortened. Two forms of resynchronization are possible. In normal operation, synchronization is carried out only with the negative edge (recessive to dominant). At low transmission speeds, synchronization can also be carried out with the rising edge (SYN = 1). t TSEG1 t PROP + t SJW + 2t Q The triple sample mode offers better immunity to interference signals. In the single sample mode a higher transmission speed is possible. For high baud rates and maximum bus length, neither SYN nor MSAM may be switched on. Bosch advises against both adjustment facilities. When an input filter matched to the baud rate or a bus driver is used, the triple sample mode is 27.5. Bus Coupling The bus coupling describes the connection of the internal signals rx (receive line) and tx (transmit line) to the pins to the CAN bus. The output pins are push/pull drivers for TLL levels. The input pins are also designed for TTL levels. Integrated transceivers (Siliconix Si9200, Philips 82C250 etc.) are available for physical coupling in the high-speed range in compliance with ISO/DIS 11898. For a laboratory system a "minimum bus" can be constructed by means of a wire-Or circuit. To utilize the advantages of differential signal transmission, an analogue comparator is necessary. 0 ITX TxD 1 tx 1 +5V 1 REF1 RxD 0 OR 0 1 rx REF0 Fig. 27-11: Bus coupling Micronas Feb. 10, 2005; 6251-579-1DS 187 CDC 32xxG-C DATA SHEET Table 27-2: Logical level transmitting ITX 0 0 1 1 tx 0 1 0 1 TxD 0 1 1 0 Bus Level Dominant Recessive Recessive Dominant inverted Remarks direct Table 27-3: Logical level receiving REF1 REF0 RxD rx Bus Level Remarks 0 0 0 1 1 1 0 1 1 0 0 1 x 0 1 0 1 x 1 1 0 0 1 0 Don't work Recessive Dominant Dominant Recessive Don't work direct inverted Bus +5V CAN +5V 1 REF1 RxD 0 OR 0 1 rx REF0 ITX TxD 0 1 tx 1 Fig. 27-12: Minimum bus 188 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 28. DIGITbus System Description 28.1. Bus Signal and Protocol The DIGITbus is a single line serial master-slave-bus that allows clock recovery from the sign stream. Data on the bus are represented by a pulse width modulated signal. There are three different signs: "0": 25% High Time "1": 50% High Time "T": 75% High Time address length is one bit. The minimum data field length is zero bit. Telegrams with more than one data field are allowed, too. For instance TTTTAAATDDDDTDDDDDTT is a valid telegram format on the DIGITbus. A telegram consisting of an address only is possible, too. The length of the data field is zero in this case. bit time T 0 1 T A data field is preceded by an address field and separated from this by a single "T". It is followed by one "T" sign. After reception of two "T" signs the telegram is finished and valid. In the idle phase (no information exchange) of the bus traffic, only the bus clock is transmitted. T Address T T T T T T A permanent high bus (100% High Time) means the bus is passive high. The bus is active if there are consecutive "T" signs, ones or zeros. A permanent low bus (0% High Time) is interpreted as bus reset or failure indicator. Reasons may be shorts or opens or even a low level forced by a bus node to indicate an internal failure or reset condition. The sign "T" is used to provide a system wide clock for the bus nodes and to separate the address and data fields and consecutive telegrams. A telegram normally consists of an address and a data field separated by one "T". These fields may be as long as necessary. Thus the length of an address or data field may carry information. The end is marked by a "T". The end of a telegram is marked by two "T" signs. T T T T T T T T T T T T After the reception of two consecutive "T" signs all bus nodes have to be prepared to receive a new telegram starting with an address field. They are ready to send an address after the reception of four consecutive "T" signs. The modification of a "T" sign to a zero or one is done by pulling the bus line to low (dominant state) at the right time. This is done by a master sending an address or a data bit or by a slave sending a data bit. In case of reading data from a slave, the master first sends the address. After receiving the address the slave waits one "T" sign and then modifies the following "T" signs to zeros and ones which the master can recognize. Slaves do not have the possibility to become active on the bus if they want to communicate a local event or if they need data from a master. It is a polling bus. Only a master is able to send an address. The master has to scan the slaves for their data. But it is possible to transfer data from one slave directly to another slave. The master has to transmit an address for which one slave is the source and the second slave is the destination. Telegrams on the bus are broadcast. Each bus node may receive them. T T Address T Data T T T One system implementation may be confined to certain address and/or data field lengths, thus reducing the hardware or software requirements. The transmitter of an address has to guarantee that the address is preceded by four "T" signs at least. An isolated data field is not possible. Each non "T" sequence, which is preceded by two or more consecutive "T" signs must be interpreted as an address. An address field is valid after the reception of the following "T". The minimum 28.2. Other Features There are two possibilities for a slave to signal a local event to the master. They are called wake-up and bus reset. level. This will awake the master who has to store this event in a flag, to start the bus clock and to scan the bus for the source of this event. The minimum low time of the reset pulse is 1/16 of the nominal bit time (1/baud rate). 28.2.1. Wake-up If the DIGITbus is passive high (permanent high level for more than one bit period) a slave may pull the bus line to low Micronas Feb. 10, 2005; 6251-579-1DS 189 CDC 32xxG-C 28.2.2. Bus Reset The rising edge of a bit or bus clock is only controlled by the bus node which generates the bus clock (clock master). No other bus node may hold down the bus line at that moment. When the clock master releases the bus line at the end of a bit, he must watch the bus line. If the bus level does not rise after at least 1/2 bit time, this must be interpreted as a protocol violation. Delay of 1/2 of a bit time is the latest moment for a master. He can indicate this protocol violation if the rising edge is delayed 1/8 bit time. Slaves may use this mechanism to signal an exception to the master. They must pull down the bus for at least 2 bit times. After such an event normal communication may be impossible until the PLL of bus nodes have synchronized again. DATA SHEET effect, the phase correction mechanism allows the bus node to adjust their internal counters. The master sends a special address to which the slave answers with a single zero. The master measures the time between the rising and the falling edge. With this value he can calculate a phase correction value and transmit it to the slave. The slave may use it to adjust his internal counter. The phase correction has to be done for each bus node separately. 28.2.4. Abort Transmission The Abort Transmission feature is an option that allows the implementation of some kind of rip cord with the DIGITbus. On an alarm event, the SW of the sending master bus node may break the current telegram and send another telegram instead. The reception of an address/data field can not be stopped. The transmission of the alarm telegram is delayed until after the end of the reception in this case. Only the actual sending bus node can abort the transmission. 28.2.3. Phase Correction On a physical bus the signal edges may be delayed by the bus load. An extra delay may be added by different trigger edges. The bus nodes see the edges at different times. This causes them to pull the bus line delayed. To compensate this 28.3. Standard Functions The following standard functions have to be included in every DIGITbus implementation. ify a received address, it is not sufficient to compare the value. The length of the address must be correct too because of the arbitrary length of the address field. 28.3.1. Send Bus Clock The Bus Clock is the sequence of "T" signs on the DIGITbus. The rising edges of the bus signal are of constant distance. Only one bus node may generate this Bus Clock even in a multimaster system. All bus nodes use this stream of "T" signs to generate telegrams. The bus clock generator knows two states. "Active Bus" means the transmission of the Bus Clock. "Passive Bus" means permanent high bus level. "Passive Bus" may be a low-power mode. 28.3.5. Send Data Every master must and some slaves are able to send a data field. A data field is preceded by an address or data field and one "T" sign. 28.3.6. Receive Data Every master must and some slaves are able to receive a data field. A data field is preceded by an address or data field and one "T" sign. It is a good idea to verify the length of a received data field if possible. But variable length data fields are possible, too. 28.3.2. Receive Bus Clock Bus nodes which do not generate the bus clock need an internal clock for their operation. They may use a separate clock source or derive their clock from the bus clock by a PLL. Bus nodes which use their own clock sources nevertheless have to synchronize on the bus clock if they want to transmit or receive data. 28.3.7. Collision Detection Collision detection together with arbitration is necessary in multimaster systems. It is necessary to avoid the disturbance of telegrams if two masters try to send a telegram at the same time. As long as both transmit the same sign (one or zero) at the same time, they don't detect a collision. If one master is sending a one and the other is sending a zero, a zero will be seen at the bus. In this case the master whose one was modified to the zero stops immediately sending. He should receive this telegram. The sender has to arbitrate his part of the telegram. Write telegram: TTTTTAAAATDDDDTTTTT Read telegram: TTTTTAAAATDDDDTTTTT The separator (T sign) after an address or data field is object of arbitration too. In a single master system arbitration loss has to be managed as a bus error. 28.3.3. Send Address The address is the first bit field in a telegram. Only a master may send this field. The sender must guarantee, that at least two consecutive "T" signs have been visible on the DIGITbus before sending this field. Therefore, he has to send four "T" signs. If one of those four transmitted "T" signs is disturbed, only one of the separated telegrams is corrupted for a receiver. Sending of an address requires synchronization on the bus clock and, in case of a multimaster system, collision detection and arbitration capability. 28.3.4. Receive Address Every slave and all multimaster-capable bus nodes must be able to receive an address. For a receiver, a valid address field must be preceded by two consecutive "T" signs. To ver- 190 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 28.4. Optional Functions The following optional functions may be designed into a certain DIGITbus implementation. 28.4.1. Abort Transmission A master who is controlling the transmission of a telegram can abort the sending of the address and data field. After four "T" signs after the last bit he can send another, more urgent telegram. If he is receiving a data field from a slave, he must wait until the slave has finished the data field. Then he can insert a new telegram. 28.4.2. Measure Pulse Width The capability to measure the pulse width of a high pulse at the DIGITbus may be used for a phase correction by some bus nodes. The bus node who generates the bus clock, sends a data read telegram to another bus node. The other bus node answers with a data field which consists of a single zero. The pulse width of this zero is measured by the master. With this value he can calculate a phase correction value and transmit it to this bus member, which may adjust its time slots to the system dependencies. 28.4.3. Correct Phase Bus nodes which do not generate the bus clock may use the above described procedure to adjust their phase. They have to answer to a special address with sending back a zero. Afterwards they will receive with another special address a correction value. With this value they can adjust the point where they pull the bus line to modify a "T" to a one or a zero. 28.4.4. Generate Wake-up If the DIGITbus is passive high (no bus clock, always high level), the clock master may be wake up by pulling the bus level to low (dominant state) for 1/16 bit time at least. All nodes without the clock master may be able to do that. 28.4.5. Receive Wake-up If there is a low pulse of at least 1/64 bit time on a passive high DIGITbus, the clock master must start to transmit the bus clock by sending "T" signs. All Masters with a bus clock generation unit must be able to do so in a system who uses this feature. 28.4.6. Generate Reset During active DIGITbus a slave may be allowed to pull down the bus line longer than up to the end of the actual bit time (2 bit times at least). The rising edge at the end of the bit will be delayed in this case. This will disturb the bus clock for all bus nodes. 28.4.7. Receive Reset The clock master is generating the rising edge at the end of a bit time. He will detect the above described reset condition and set a flag if the rising edge is delayed for at least 1/8 of the bit time. Micronas Feb. 10, 2005; 6251-579-1DS 191 CDC 32xxG-C DATA SHEET 192 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 29. DIGITbus Master Module The DIGITbus is a single-line serial master-slave-bus that allows clock recovery from the sign stream. The address and data field are of arbitrary length. The DIGITbus master module is a HW module for connecting a single-chip controller to the DIGITbus. It generates the bus clock and manages short telegrams autonomously. Transmission and reception of long telegrams is supported by a FIFO each. The DIGITbus master may be used in a single or in a multimaster bus system. Features - Single master in a single-master system. - Clock master in a multimaster system. - Passive master in a multimaster system. - Bus clock generation. - Receive and transmit a telegram with address and data field. - Transmit FIFO and receive FIFO. - Collision detection and arbitration. - Abort transmission. - Sleep mode. - Bus monitor mode. - Measure pulse width for phase correction. - Phase correction. - Receive wake-up and bus reset signal. - Register interface to the CPU. 29.1. Context Apart from reset and clock line, the interface to the CPU consists of registers connected to the internal address and data bus. An output signal may be connected to the interrupt controller. A modified universal port builds the output logic which is connected with its special input and output to the DIGITbus master. This provides an easy way for the SW to hold the bus line permanently low or high, or to investigate bus level directly, without support of DIGITbus Master HW. An open drain output instead of a push/pull output is necessary for the universal port to build a single-line wired and bus. HW Option clock ADB R/W DB Reset Interrupt DIGITbus Master rx tx Universal Port with Open Drain Output SI SO Port Pin +U DIGITbus Other Transmitters Fig. 29-1: Context diagram, single pin bus HW Option clock ADB R/W DB Reset Interrupt tx SO Universal Port with Push/Pull Output DIGITbus Master rx Universal Port SI Port Pins 1 e.g. MOSFET External protection circuit +U DIGITbus Other Transmitters Fig. 29-2: Context diagram, double pin bus Micronas Feb. 10, 2005; 6251-579-1DS 193 CDC 32xxG-C 29.2. Functional Description 29.2.1. 3-bit Prescaler The programmable 3-bit Prescaler supplies the module with clock signals. It scales down the HW option selectable clock by factor 1, 2, 3 to 8 (see Table 29-2 on page 196). The output is 64 times the bus clock. The desired input frequency from the clock divider is hardware-programmable. DATA SHEET 29.2.8. Collision Detection The collision detection logic compares each incoming with the actual outgoing bit. A difference is signaled to the send telegram logic. If the module is transmitting, the send telegram logic is stopped immediately and the transmit FIFO and shift register are flushed. 29.2.2. Internal Clocks In low power mode the clock supply of the whole module with exception of the receive bit logic can be stopped. The receive bit logic needs a clock in low power mode too, because it must filter and watch the bus line for a wake-up signal. 29.2.9. Transmit FIFO The transmit FIFO has five entry addresses. One for the field length of address or data field, one for a address byte, one for a data byte, one for more address bytes and one for more data bytes. The field length has to be written once before the corresponding field is entered into the FIFO unless the field length is not a multiple of 8. An entry into the address register is inserted into the bus clock after the reception of 4 consecutive T-signs. An entry into the data register is inserted into the bus clock after the reception of a non T-sign and one T-sign. Thus it is possible to append a second data field (maybe acknowledge) after the reception of a telegram. The transmit FIFO may be flushed to abort a transmission. It is also flushed if the transmit telegram logic is active and a collision is detected. 29.2.3. Transmit T The transmit T logic sends a continuous stream of T-signs if active. It outputs a permanent high if it is inactive. 29.2.4. Transmit Bit Depending on the input signals the transmit bit logic modifies the T-signs to ones or zeros. A phase correction can be done by adjusting the start time of a transmit bit sequence. Other bus behavior than sending zeros, ones or T-signs may be forced by the SW using the universal port in normal mode directly. The bus line may be released or pulled low. 29.2.10. Receive FIFO The receive FIFO will be filled from the receive shift register. It has two exit addresses. One for the field length and field type and one for the bit field. The field length has to be read before the corresponding field is taken from the FIFO. The receive FIFO will be frozen if it is full. The receive shift register will be overwritten. 29.2.5. Receive Bit The receive bit logic samples the bus level at a frequency of 64 times of the bus clock. It filters the input signal and decodes the input stream to supply the receive telegram logic with the logical bus signals (0, 1 and T) and the receive clock. Additional it measures the pulse width of each non Tsign. It creates a bus reset signal if the active bus is hold down beyond the end of a bit time. It creates a wake-up signal if there is a low level on the passive high bus. 29.2.11. Interrupt Several flags of the status registers are connected by a logical-or to the interrupt source signal. The interrupt output can be masked by a flag in the control register. 29.2.6. Send Telegram The send telegram logic will be enabled by the transmit FIFO and the receive telegram logic if four consecutive T-signs were received. It supports the transmit bit logic with the transmit bit sequence. If it recognizes the beginning of a new field, it waits one bit time (separator T-sign). 29.2.7. Receive Telegram The receive telegram logic traces the bus and indicates the state to the status register and other related modules. The received bit field is written to the receive FIFO. The receive telegram logic is active all the time. Even if the module is transmitting a telegram, all bits must also be received in a multimaster system, because arbitration may be lost. Reception of own telegrams can be disabled (in a single-master system). 194 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C ADB R/W Address Decoder DIGITbus Master run HW option fDB 3-Bit-Prescaler DIGITbus Interrupt Source Control/Status T-Seq. DB Phase Tx Field Length Tx Addr. Field Tx Data Field Reset Tx More Addr. Field Tx More Data Field wake-up/bus reset arbitration lost busy full flush T dat Transmit Telegram TxSR rise Collision Detection & 0-Seq. 64 x bus clk 1-Seq. tx 64 x bus clk generate bus clock Transmit T Transmit Bit TxFIFO RxSR rx external only Receive Telegram rxclk data lost RxFIFO empty T dat txclk Receive Bit rx Rx Field Length Rx Field 64 x bus clk Pulse Width Fig. 29-3: Block diagram Micronas Feb. 10, 2005; 6251-579-1DS 195 CDC 32xxG-C 29.3. Registers The register mnemonic prefix "DG" stands for DIGITbus. PSC r/w: Prescaler Scaling value DATA SHEET Table 29-1: Register mapping Table 29-2: Clock prescaler Addr. Offs. 0 1 2 3 4 5 6 7 Mnem. DGC0 DGC1 DGS0 DGRTMD DGTL DGS1TA DGTD DGRTMA Status 1 reserved Rx Field Rx Length readable writable PSC Control 0 Control 1 0x0 Status 0 0x1 Tx More Data 0x2 Tx Length 0x3 Tx Addr. 0x4 Tx Data 0x5 Tx More Addr. 0x6 An "x" in a writable bit location means that this flag is reserved. The user has to write a zero to this location for further compatibility. An "x" in a readable bit location means that this flag is reserved. A read from this location results in an undefined value. 0x7 7 8 8.9 7.8 11.2 9.8 22.3 19.5 6 10.4 13.0 26.0 5 12.5 15.6 31.25 4 15.6 19.5 39.1 3 20.8 26.0 52.1 2 31.25 39.1 78.1 1 62.5 78.1 156.25 Divide by Bus Clock in kHz fDB = 4 MHz fDB = 5 MHz fDB = 10 MHz Note: With an input clock of 5 MHz, the bus clock frequency of 31.25 kHz and its derivatives (16, 8, 4, 2, 1 kHz) cannot be achieved. Thus, with a 5 MHz quartz the DIGITbus should be operated in PLL mode. DGC0 7 r/w RUN 0 Control Register 0 6 GBC 0 5 ACT 0 4 RXO 0 3 X x 2 1 PSC 2 to 0 0 DGC1 7 6 ENEM 0 Control Register 1 5 ENOF 0 4 x x 3 2 PHASE 1 0 0 0 0 Res r/w INTE 0 RUN Run r/w1: Module clock is active. r/w0: Module is not clocked. The module is absolute inactive if RUN is zero. Other flags are not functional then. GBC r/w1: r/w0: Generate Bus Clock Module generates bus clock No bus clock 0 0 0 0 Res INTE r/w1: r/w0: ENEM r/w1: r/w0: ENOF r/w1: r/w0: Enable Interrupt Enable interrupt Disable interrupt Enable Not Empty Interrupt Enable Disable Enable Not Full Interrupt Enable Disable ACT Activate r/w1: Module is active (reception and transmission). r/w0: Module is sleeping (low power mode). Only the receive bit logic is active in low power mode. RXO r/w1: r/w0: Receive External Only Don't receive own telegrams. Receive all. PHASE Phase Correction Field r/w: Transmit phase. The start of the transmit frame can be selected in increments of 1/64 of a total bit time related to the rising edge. Values between 0 and 15 are possible, but only the interval from 0 to 9 results in correct behavior. Set PHASE to 2 if the DIGITbus is operated as clock master (GBC = 1). This is necessary to compensate for internal delay of 2 clocks. Refer to section 29.4.10. for further information on phase correction. 196 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Bit time Transmitted 0 16 32 48 0 RxFIFO NEM 0 16 32 48 0 Received Phase delay Corrected 4 16 32 48 0 Interrupt PHASE = Start value of transmit counter. TxFIFO Fig. 29-4: Phase correction EMPTY NOF DGS0 7 w r x RDL x Status Register 0 6 x NEM 0 5 x NOF 1 4 TGV 3 PV 2 ERR 1 x 0 ARB Interrupt Fig. 29-5: Rx- and TxFIFO timing Res 0 0 0 x 0 RDL Receive Data Lost r1: Data lost r0: No data lost This flag is set if the receive FIFO is full and the shift register tries to store its contents to the FIFO because a new bit arrives. In this case the FIFO is frozen but the shift register is overwritten. It must be interpreted and cleared by the user. It is cleared by reading an entry from the FIFO. NEM Rx FIFO is Not Empty r1: There is at least one entry to read. r0: Empty. (see Fig. 29-5 on page 197) NOF Tx FIFO is Not Full r1: There is at least one entry free. r0: Full. It generates only an interrupt in the moment when the limit is passed. It does not generate interrupts when the FIFO is empty (see Fig. 29-5 on page 197). TGV Telegram Valid r1: Telegram valid r0: Telegram not valid w0: Clear flag This flag will be set if two consecutive T-signs were received. It is reset by the HW if a non-T-sign is received. It can be cleared by the user if the related telegram is evaluated. PV r1: Protocol Violation Wake-up if bus is passive high. Bus reset if bus is active. r0: No trouble w0: Clear flag It must be interpreted and cleared by the user. It is set when the receive bit logic enters or leaves state passive high or when it enters the state passive low. ERR Error r1: Fatal error. r0: No error w0: Clear flag The HW sets this flag either if a dominant level is transmitted and a recessive level is detected (collision error), or if there was a wrong edge within a received bit. If a collision error is detected during transmission, the flag ARB will also be set and transmission stops immediately. This flag has to be cleared by the user. ARB Arbitration Lost r1: Arbitration lost. r0: No arbitration loss. w0: Clear flag This flag will be set if a collision is detected during transmission. It must be cleared by the user. The transmit buffer is flushed if ARB is true. It is impossible to write to the transmit FIFO as long as ARB is true. Wait until flag TGV is true before reloading TxFIFO. This is automatically done if ARB is evaluated within the TGV interrupt subroutine only. The flags RDL, NEM, NOF, TGV, and PV trigger the interrupt source signal (see Section 29.4.8. on page 201). DGS1TA 7 w r 0 STATE 1 Status 1 & Tx Address Register 6 5 4 3 2 1 0 Transmit Address PW5 to 0 0 0 0 0 0 0 Res The first byte of an address field must be written to DGS1TA. Micronas Feb. 10, 2005; 6251-579-1DS 197 CDC 32xxG-C STATE r: Bus State State of receive bit logic. DATA SHEET Table 29-4: LEN usage, receive and transmit length LEN 210 1 2 3 4 5 6 7 0 001 010 011 100 101 110 111 000 Valid Bit Numbers 76543210 _______x ______xx _____xxx ____xxxx ___xxxxx __xxxxxx _xxxxxxx xxxxxxxx Table 29-3: Receiver states STATE 00 01 10 11 Bus Passive low Passive high Active low Active high PW Pulse Width r: Pulse width The pulse width of the most recent non-T-sign is stored in this register. It is measured in increments of 1/64 of the bus clock period. DGRTMD 7 w r RDL 0 NEM 0 Rx Length & Tx More Data Register 6 5 4 3 2 1 0 The examples in Table 29-5 illustrate the interpretation of register DGRTMD. They are valid for an address field (FTYP = 1) or a data field (FTYP = 0). Table 29-5: DGRTMD interpretation examples EOFLD 1 0 1 0 Last byte of a field. The six right most bits belong to the field. A byte of a field. All bits belong to the field. At least one byte follows. Last byte of a field. Eight bits belong to the field. Impossible. Transmit More Data FTYP x EOFLD x x x x LEN2 to 0 x x Res More bytes of a data field must be written to DGRTMD. The read part of register DGRTMD is associated with the front entry in the receive FIFO (the receive field DGRTMA). It has to be read and interpreted before the corresponding FIFO entry. RDL Receive Data Lost r1: Data lost r0: No data lost The flag RDL from the status register DGS0 is mirrored here. It is cleared by a read access to register DGRTMA. NEM Receive FIFO is Not Empty r1: There is at least one entry. r0: Empty The flag NEM from the status register DGS0 is mirrored here. FTYP, EOFLD, LEN and register DGRTMA are not valid if NEM is false. FTYP r1: r0: Field Type Address field Data field LEN 6 0 0 0 DGRTMA 7 w r x x Rx Field & Tx More Address Register 6 5 4 3 2 1 0 Transmit More Address Receive Field x x x x x x Res EOFLD End of Field r1: Last byte of a field r0: Not last byte of a field If EOFLD is set, the corresponding FIFO entry is the last part of the actual field. The next entry, if there is one, belongs to a new field. LEN Length of Field r: Length of valid data bit The three-bit length does not limit the overall length of the corresponding field. The length field defines how many bits of the front entry of the receive FIFO carry valid bits. They are right aligned (Table 29-4). The real length of the field is unlimited. The user must count the bytes he fetched from the FIFO to calculate the real field length. More bytes of an address field must be written to DGRTMA. The bytes of a received field must be read from register DGRTMA. The meaning of this field (address or data) is defined by the flag FTYP. Received bytes of a bit field are right-aligned. The last byte of a long bit field (with the LSB) may be filled partially. To get the whole bit field right-aligned, it is necessary to shift all preceding bytes to the right. A read access to this register takes the top entry of the receive FIFO. Both registers DGRTMA and DGRTMD are overwritten by the next FIFO entry as result of a read access. 198 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C wait until EMPTY or TGV becomes true before rewriting TxFIFO. Setting of FLUSH clears TGV at the same time. 0 DGTL 7 w x x r BUSY 0 Transmit Length Register 6 FLUSH 0 EMPTY 1 5 x x x x 4 x x x x 3 x x x x 2 1 LEN2 to 0 EMPTY r1: r0: Res Tx FIFO is Empty No transmit telegram in FIFO. Transmit telegram in FIFO. 0 x x 0 x x 0 x x Res The transmit length register is associated with the whole field (address or data) which will be written into the transmit FIFO. It has to be written before the first entry of the field. BUSY Transmitter is Busy r1: Busy. r0: Idle. This flag is true as long as there is an entry in the TxFIFO or transmission is not completed. It is set with the first entry into the TxFIFO and reset after the transmission of the first T-sign after a telegram. FLUSH Flush Tx FIFO w1: Empty Tx FIFO and abort transmission. w0: No action. This flag will be reset by the HW autonomously. After FLUSH LEN Length of Field w: Length of address or data field. These three bits correspond to the first byte of a bit field. They define how many bits of this byte carry valid information and should be transmitted (see Table 29-4 on page 198). DGTL must be written before the first byte of the actual bit field is written to the FIFO. It has only to be written once for each bit field. The overall length of the bit field is not limited. DGTD 7 w x x Transmit Data Register 6 5 4 3 2 1 0 Transmit Data x x x x x x Res The first byte of a data field must be written to DGTD. The first byte of a bit field (with the MSB) which is entered into DGS1TA or DGTD, may be partially filled. In the following bytes, all bits must contain valid data. 29.4. Principle of Operation 29.4.1. Reset The module reset signal resets all registers and internal HW. The standby bit in a standby register does the same. Setting flag RUN in register DGC0 resets all internal HW and registers with exception of registers DGC0, DGC1, DGS0 and DGS1TA. These registers are accessible all the time, they are not reset by any setting of the DIGITbus Master flags. Internal HW are reset to an inactive state (not transmitting, not receiving). Internal counters are reset to zero. FIFOs and shift registers are empty. Internal representations of the bus line are reset to passive bus level (high). 29.4.2. Hardware Settings The DIGITbus clock and the source of the DIGIT-IN input signal can be set by HW Options (See table 29-6). Refer to section "HW Options" for setting them. 29.4.3. Initialization Prior to operation, proper SW configuration of the U-Ports assigned to module DIGITbus as input and as double pulldown output has to be made. Be aware that it is possible to have DIGITbus input and output on the same port pin for easy design of a serial wired-or bus (single-pin bus, Figure 29-1), or to have input and output on separate port pins which allows a design of an input protection circuit (double pin bus, Figure 29-2). See table 29-6 and section "Ports" for details. After reset and after setting flag DGB in standby register SR0, the DIGITbus master is inactive. The global enable flag RUN must be set together with the appropriate prescaler entry PSC, to activate the module. For the effect of CPU clock modes on the operation of this module refer to section "CPU and Clock System" (see Table 4-1 on page 41). 29.4.3.1. Clock Master The flag GBC (generate bus clock) must be set, if the DIGITbus master should generate the bus clock. The module acts now as clock master of the connected DIGITbus system. It outputs a stream of T-signs. Registers DGC0 DGC1 reset Internal HW and remaining registers SR0.DGB reset RQ DGC0.RUN reset RQ Fig. 29-6: Reset structure Micronas Feb. 10, 2005; 6251-579-1DS 199 CDC 32xxG-C Table 29-6: Module-specific settings Module Name HW Options Item Address DC Initialization Item Setting Enable Bit DATA SHEET Table 29-7: Operating modes RUN 0 1 GBC x 0 ACT x x RXO x x Remarks Standby mode Passive master. External bus clock generation is necessary. Clock master Sleep mode Active mode Receive all. (Recommended in multi master system) Receive external only. (Recommended in single master system) DIGIT- Clock bus DIGIT- U2.6 spe- SR0. DGB OUT cial out, double pull-down mode (single pin bus) or special out (double pin bus) DIGIT- U2.4 (speIN cial in) or U2.6 (special out) 1 1 1 1 1 0 x x x 0 1 1 x x x 0 Input PM.CACO 1 x 1 1 29.4.3.2. Receiver/Transmitter Setting the flag ACT activates the receive and transmit logic. From now on all telegrams are received in the receive FIFO. Writing to the transmit FIFO initiates transmission of a telegram. The bus clock (T-signs) must be activated some time before the first telegram is transmitted. This is necessary, because other modules may use a PLL for generating the internal clock from the bus clock. No telegram shall be transmitted before all modules have locked on the bus clock. 29.4.3.3. Single Master System In a single-master system (no collision possible), you can suppress reception of transmitted telegrams by setting flag RXO (receive external only). This unburdens the CPU from clearing the receive FIFO of those telegrams. 29.4.3.4. Multimaster System In a multimaster system it is necessary that each transmitted telegram is received too, because arbitration may be lost and then the transmitter becomes a receiver. If arbitration was not lost, the receive FIFO must be read to empty it. The flag RXO has to be cleared in a multimaster system. A new address field is transmitted if there are at least 4 consecutive T-signs on the bus. A new data field is transmitted if there was exactly one T-sign. If the last bit of a field was transmitted and there are no more entries in the transmit FIFO, the transmitter stops sending. After reception of two consecutive T-signs the telegram valid flag TGV is set. This is the signal for the SW to evaluate whether transmission was correct or whether an arbitration loss or an error canceled transmission (flags ARB, PV and ERR). In the latter case SW must initiate retransmission. A telegram has been transmitted correctly, if ARB and ERR are false and EMPTY is true. Transmission starts with the first entry in the transmit FIFO. Consecutive fields should be entered before the transmission of the preceding field is finished. Take care about possible interrupts. 29.4.4.1. Transmit FIFO SW must ascertain that there is an empty entry in the transmit FIFO before writing to it. Flag NOF (not full) indicates that there is at least one entry free. Flag EMPTY indicates complete emptiness of transmit FIFO. After reset, FLUSH or ARB wait until flag TGV is true before rewriting TxFIFO. Short telegrams can completely be buffered in the FIFO. Managing long telegrams is a SW job. The SW must buffer long telegrams and write the parts in time. The transmit FIFO is intended to unburden the CPU from immediately reaction on an NOF interrupt. If an entry becomes free, the SW has time to write, as long as it needs to transmit two FIFO entries and the contents of the transmit shift register. This time must not necessarily be the duration for sending 24 bit. Maybe only one bit of each remaining FIFO entry has to be sent. The transmit FIFO is not intended for telegram tracking. Only one transmit telegram at a time must be entered. 29.4.4. Transmission Transmission is initiated by writing a telegram into the transmit FIFO. If the field length is not a multiple of 8 bit, the total field length modulo 8 has to be written to register DGTL. This must be done once for each field and before any entry to registers DGS1TA, DGTD, DGRTMA or DGRTMD. If the total field length is a multiple of 8 it is not necessary to write the field length to register DGTL. The first entry of a field (address or data) has to be written right-aligned to register DGS1TA (address) or DGTD (data). Further entries of the same field, if it is longer than 8 bits, have to be written to DGRTMA (more address) or DGRTMD (more data). A telegram is transmitted MSB first, hence fields have to be written to transmit FIFO MSB first. 29.4.5. Reception Every non-T-sign is shifted into the receive shift register. If it is full or if a T-sign is received, the shift register is stored into the receive FIFO. This is done until the receive FIFO is full. 200 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 29.4.8. Interrupt Five flags (RDL, NEM, NOF, TGV, PV) are connected to the interrupt source output by an or operation. This output can be enabled globally by flag INTE. The interrupt generation of two flags (NEM, NOF) can be enabled locally by flags ENEM and ENOF. A rising edge of a flag triggers the interrupt source output. In this case, the FIFO is frozen, but the shift register continues operation. The flag RDL indicates the latter case. If the shift register is stored to the receive FIFO because a T-sign was received, the corresponding flag EOFLD is set, indicating that this is the last entry of a field. The corresponding flag FTYP is modified at the same time. If two or more consecutive T signs were received in front of the actual field, it is set, indicating that this field has to be interpreted as an address field. If only one T-sign has been received in front of the actual field, it is cleared, indicating that it has to be interpreted as a data field. The flag TGV is set if two consecutive T-signs were received. This is the moment to read status flags and Receive FIFO. The flags PV and ERR have to be interpreted. Even if an error occurred, the Receive FIFO must be emptied by reading it because every telegram or fragment is stored there. Otherwise reception of the next telegram may overflow the receive FIFO, which is indicated by flag RDL. Every time you want to read DGRTMA, it is ingenious to read DGRTMD first, because DGRTMD and DGRTMA are overwritten with a read access to DGRTMA. 29.4.5.1. Receive FIFO The receive FIFO contains entries as long as flag NEM is true. Short telegrams can be buffered completely in the receive FIFO. SW must buffer long telegrams and read parts of it in time. INTE RDL ENEM NEM ENOF NOF TGV PV & OR & & DIGITbus Interrupt Source Fig. 29-7: Interrupt Sources 29.4.9. Measure Pulse Width The pulse width (high time) of every non-T-sign is stored with the falling edge of the bus signal in status register DGS1TA in the field PW. T-signs do not affect PW. It must be read before the falling edge of the next non-T-sign. 29.4.6. Sleep Mode Only the receive bit logic is active in sleep mode. Neither transmission nor reception of telegrams is possible. A wake-up (passive high to low edge) is signaled by flag PV. The DIGITbus master is not automatically activated by a wake-up. This has to be done by SW. The flag PV can be used to trigger an interrupt. Switching to Sleep Mode while a telegram is transmitted can cause problems. Hence make sure, that bus clock generation is switched off only if bus is idle (T-signs). 29.4.10. Correct Phase The rising edge of the bus signal can be delayed by inner (sampling and filter) or outer (bus load) influences. This delayed rising edge resets a 6-bit transmit counter in the transmit bit logic. The transmit counter pushes the bus line low when it reaches 15 (transmitting 0) or 31 (transmitting 1). It releases the bus line when it reaches 55. The transmit counter is reset to a value which contains two zeros at the most significant position and the four PHASE bits of the control register DGC1 at the least significant position. This allows an adjustment of the transmitted non-Tsigns between 0 and 15/64 of the whole bit length. 29.4.7. Abort Transmission Writing a one to flag FLUSH aborts the transmission of a telegram after completion of the actual transmitted bit, if the DIGITbus master is the transmitter. The transmit FIFO is emptied and another, more urgent telegram can be transmitted. Transmission of the new telegram starts, as soon as 4 consecutive T-signs were received after the aborted telegram. Flag TGV is cleared with a FLUSH. This is the reason why TGV is set (and interrupt is triggered if enabled) after reception of 2 T-signs, even if no telegram was aborted by FLUSH because it happened during transmission of T-signs. Resetting of flag TGV is the reason why an aborted address field is marked as data field (FTYP = 0) in the RxFIFO. It is not possible to abort a telegram or a field which is transmitted by another bus node. 29.4.11. Error The setting of flag ERR may have one of the following causes: - Wrong baud rate of DIGITbus Master or other bus nodes. - Wrong port configuration of DIGITbus Master. - Disturbances on bus line. - HW of DIGITbus Master is damaged. 29.4.12. Precautions Do not access DIGITbus registers in CPU Slow and Deep Slow mode. This can cause interrupts. If fXTAL is 5 MHz, a bus clock of 31.25 kHz is possible only in PLL mode (Table 29-2). Micronas Feb. 10, 2005; 6251-579-1DS 201 CDC 32xxG-C 29.5. Timings DATA SHEET Bus Clock Tx stream txa Rx stream TGV NEM ARB collision Fig. 29-8: Tx timing D T T T T T A A T D D T T T T D T T T T T A A T D D T T T T Bus Clock Tx stream txa Rx stream TGV NEM ARB collision D T T T T T A A T D D T T T T D T T T T T T T T T T T T T T Fig. 29-9: Rx timing 202 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 30. Audio Module (AM) The audio module (AM) provides a gong output signal that may be used to drive a speaker circuit. The output signal is a square wave signal with selectable gong frequency. The gong signal amplitude is defined by the pulse width of a PWM signal. An internal accumulator is selectable to automatically decrease this pulse width and thus the gong amplitude following an exponential function. Features - Programmable gong frequency - Programmable gong duration - Programmable initial amplitude - Gong can be stopped and retriggered - Generation of an exponentially decreasing gong amplitude function without CPU interaction 1 13 /32 13 + Adder 13 '0x1F' Data Bus Write AMAS (Start/Stop gong sound) 13 13 5 8 LSBs AMAS Amplitude - Latch (13 Bit) MSB 13 8 Read AMAS SQ R Data Bus (Bit 7) AMA U 1.3 AM-PWM & COMP Amplitude=0 ? HW Option AC AM Clock 8 FAMClock & AMMCA 8 Bit - PWM VDD 0 AM Trigger U 1.4 AM-OUT 8-Bit Counter CLK Clear Counter Set Prescaler-Register & FPWM 7-Bit Counter CLK 1/ 2n Clear Counter Set Frequency-Register 7 FGong 5-Bit Counter CLK 1n /(2 ) Clear Counter Set Decrement-Register 3 FDecrement 8 Write AMPRE Data Bus AMA Write AMF Data Bus Write AMDEC Data Bus Fig. 30-1: Block diagram of the audio module Micronas Feb. 10, 2005; 6251-579-1DS 203 CDC 32xxG-C 30.1. Functional Description The audio module output frequency is defined by the following equations: Frequency: F AMTrigger F AMClock F Gong = -------------------------------- = ----------------------------------------------------------------2 ( AMF + 1 ) 2 ( AMF + 1 ) ( AMPRE + 1 ) DATA SHEET GDF ln 0,5 - ln AMAS 2 t d ----------------------------------------- ---------------F Gong 1ln 1 - ----- 32 Amplitude: ( AMAS + 1 ) Ampl. ---------------------------------( AMPRE + 1 ) where the maximum amplitude is 1 if AMAS is equal to or bigger than AMPRE. In the latter case the amplitude remains constant until the decay mechanism has decreased AMAS below AMPRE. Duration: AMF, AMPRE, AMAS and GDF are register values and described later. The initial gong sound amplitude is set by writing the Audio Module Amplitude & Status Register (AMAS), this write also starts the gong sound. An active audio module is indicated by the read-only audio module active bit (AMA) in the AMAS. Every 1st..32nd cycle of the gong sound frequency (depending on the gong duration factor (AMDEC.GDF) a new amplitude value is calculated (FDecrement). The falling edge of the amplitude decrement frequency FDecrement is latching the output of the adder into the amplitude latch (13 Bit) and simultaneously the 8 MSBs into the PWM. ment During the first low cycle of FGong following the active FDecreedge the PWM is already running with the newly calculated amplitude, but takes effect at the output not until the next high cycle of FGong. FGong is modulating the PWM-output to generate the gong sound frequency, while the decreasing PWM-value generates an exponential decreasing amplitude. As soon as the 8 MSBs of the amplitude latch are reaching zero, the AMA will be reset, which deactivates the audio module. The sound is generated by blocks of pulses 2 x AMF x AMPRE -> FGong AMF x AMPRE AMPRE AMAS (PWM) One block of pulses Fig. 30-2: Sound generation 30.1.1. Hardware Settings The AM clock frequency FAMClock is set by HW option AC. For the effect of CPU clock modes on the operation of this module refer to section "CPU and Clock System" (see Table 4-1 on page 41). 30.1.2. Initialization Prior to entering active mode, proper SW initialization of the ports has to be made. The ports have to be configured special out. Refer to "Ports" for details. Three audio module registers have to be set before the gong sound can be started: the gong prescaler (AMPRE), the gong sound frequency (AMF) and the gong duration factor (AMDEC.GDF) register. 30.1.3. Start Gong The gong sound is started by writing the initial amplitude value into AMAS. Simultaneously with the write to AMAS the Flag Audio Module Active (AMA) is set, which enables the FAMClock-input. 30.1.4. Restart Gong It is possible to restart the gong sound simply by writing a new initial amplitude value to AMAS independent of the former initial value or the current value of the register. (Note: 204 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C To stop the gong sound, just write 0x00 into AMAS. The gong sound then will stop immediately with the writing of 0x00 (also indicated by AMA). A continuous tone will never stop automatically. It has to be stopped by writing 0x00 into AMAS. The current amplitude value cannot be read out). The new gong sound will start immediately with a low cycle of FGong. 30.1.5. Stop Gong The gong sound will stop automatically as soon as the amplitude value in AMAS reaches zero. This will reset the AMA, which indicates the inactive audio module. Conditions: (FPWM = 15.625 kHz; FGong = 601 Hz; AMDEC value = 2, FDecrement = 150.25Hz) A 100 % zoomed gong output signal after 0 s (initial) B 50 % after 0.146 s (0.68) FPWM PWM Pulse Duty Factor 0 1 2 3 12 13 14 FGong 15 25 26 C 15 % after 0.398 s (1.87) 4x A Gong Output Pin FGong 4x B 4x C FDecrement start gong time 0s 0.146 s (0.68) 0.398 s (1.87) new amplitude (n.a.) n.a. n.a. n.a. n.a. Fig. 30-3: Example sections of the audio module output signal 30.1.6. Decay of Sound The decay characteristic used for this gong sound is described by the following exponential function: An A0 (1 - 1/32)n with A0 = initial amplitude (AMAS) An = amplitude after n FDecrement cycles n = int (t * FDecrement) = number of decrement cycles Each FDecrement cycle the amplitude is decreased by 1/32. FDecrement is determined by the value of GDF in the register AMDEC and by FGong: F GONG F Decrement = --------------------GDF 2 GDF = 0...5 With GDF settings of 6 and 7 the gong sound amplitude update frequency FDecrement is zero (continuous tone). The time constant of the above exponential function is defined as the time interval within which the amplitude A is decreasing to 36.8%. Following the above formula, n can be expressed as ln A n - ln A 0 n -----------------------------1 1 - ----- ln 32 Micronas Feb. 10, 2005; 6251-579-1DS 205 CDC 32xxG-C Given n 1- 1 - ----- 0, 368 = 32 the number n of FDecrement cycles needed to reduce the initial amplitude to 36.8% is n 32 With an initial amplitude of 0xFF the total time t255->0 needed to reach zero amplitude in the 8 Bit - AMAS is n = 193 FDecrement cycles, which is approximately 6. With an initial amplitude lower than 0xFF the gong sound duration is shorter. That means that is correlating with FDecrement. The higher FDecrement, the shorter is. The total time from a start amplitude A0 to an end amplitude An is approximately calculated according to following formula. ln A n - ln A 0 2 GDF t A A ------------------------------ -------------------F GONG 10 n ln 1 - ----- 32 To sum up, it can be said that the total duration of the gong sound depends on FGong, set with AMF and AMPRE, the setting of the gong duration factor GDF and the setting of the initial amplitude AMAS. DATA SHEET 206 Feb. 10, 2005; 6251-579-1DS Micronas . Micronas 56 64 72 80 88 96 104 112 120 128 136 144 152 160 168 176 184 192 200 time DATA SHEET AMAS (MSB of amplitude latch) 260 Decay of Sound - Function 240 220 200 180 160 140 120 Feb. 10, 2005; 6251-579-1DS 100 36.8% 80 60 40 13.5% 20 5.0% 1.8% 8 16 24 32 40 48 1/FDecrement 1 2 3 4 5 6 no. FDecrement-cycles CDC 32xxG-C 207 CDC 32xxG-C 30.2. Registers DATA SHEET AMAS 7 w r AMA 0 x x Audio Module Amplitude and Status Register 6 5 4 3 2 1 0 Note stop, frequency, duration) is the same. The tone is started by writing an initial value to AMAS, but this value will only influence the duration of the tone, not its amplitude. GDF Gong sound Duration Factor Initial Amplitude x x x x x x x x x x x x Res This register sets the gong sound duration in dependence of FGong. With GDF=0 the amplitude will be decreased every FGong - cycle, values 1 to 5 will result in an amplitude update frequency of FGong / 2 to FGong / 32 according to this equation: F GONG F Decrement = --------------------GDF 2 GDF = 0...5 Initial Amplitude A write access to this register starts or stops the gong sound, while the value written is the initial amplitude. Writing the value 0x0 into this register during an active gong sound deactivates the gong sound immediately, while writing a value > 0x0 is restarting the gong sound immediately with the new Initial Amplitude. wnn: (Re-)Start gong sound with initial amplitude. w00: Stop gong sound. AMA Audio Module Active Flag This flag indicates an active Audio Module generating a gong sound. r1: Audio Module is active. r0: Audio Module is not active. A value of 6 or 7 disables decrease of the amplitude, so a continuous tone with the initial amplitude will be generated (FDecrement = 0). To stop the continuous tone write a 0x00 to AMAS or change the gong sound duration factor to let the tone decay. It is possible to change GDF during an active gong sound (AMA = '1'). Table 30-1: Definition of GDF GDF 0x0 gong sound duration factor 1 2 4 8 16 32 continuous tone AMF 7 w x 0 Audio Module Frequency Register 6 5 4 3 2 1 0 Note 0x1 0x2 0x3 Res Sound Frequency 0 0 0 0 0 0 With this register the gong sound frequency is programmed. The PWM frequency is divided by twice the register value increased by one. The value which has to be written, resp. the resulting gong sound frequency is calculated with: F AMTrigger AMF = -------------------------------- - 1 2F GONG It is possible to write a new gong sound frequency during an active audio module (AMA = '1'). 0x4 0x5 0x6 0x7 AMPRE 7 w Audio Module Prescaler 6 5 4 3 2 1 0 Note Prescale Value 1 1 1 1 1 1 1 1 Res AMDEC 7 w AMMCA 0 Audio Module Decrement Register 6 x - 5 x - 4 x - 3 x - 2 1 GDF 0 Note 0 0 0 Res AMPRE defines the frequency of the trigger input of the Audio Module. The AM clock input is divided by the Prescale Value plus one to derive the trigger frequency FPWM. F AMClock AMPRE = ------------------------------ - 1 F AMTrigger AMPRE must be greater than zero. AMMCA w1: w0: Audio Module Maximum Constant Amplitude Flag Activate the AMMCA mode. Deactivate the AMMCA mode. With the flag AMMCA the audio module maximum constant amplitude mode is selected. If this flag is set, the gong sound with the maximum, not decreasing amplitude is available at the audio module output pin. The only difference between this tone and a 'normal' gong sound is the constant, not decreasing amplitude. The handling of this tone (i.e. start, 208 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 31. Hardware Options 31.1. Functional Description Hardware Options are available in several areas to adapt the IC function to the host system requirements: - clock signal selection for most of the peripheral modules from f0 to f0/217 plus some internal signals (see Table 31-3 on page 210) - special out signal selection for some U- and H-ports - Rx/Tx polarity selection for SPI and UART modules Hardware option setting requires two steps: 1. selection is done by programming dedicated address locations in the HW options field (see Section 31.2. on page 209) with the desired options' code (see Section 31.3. on page 210). 2. activation is done by copying the HW options field to the corresponding HW options registers (see Section 31.3. on page 210) at least once after each reset. In EMU and MCM devices all HW options are SW progammable. In mask ROM derivatives the clock options are hard-wired according to the HW options field of the ROM code hex file. Those options can only be altered by changing a production mask. To ensure compatible option settings in MCM and mask ROM derivatives, when run with the same ROM code, it is mandatory to always write the HW options field to the HW option registers directly after reset. 31.2. Listing of Dedicated Addresses of the Hardware Options Field Please refer to section "Memory and Special Function ROM System" for the dedicated start address of the HW options field. Table 31-1: HW Options Field Offs. 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F Mne. PF0C SMC SP0C SP1C SP2C P9C P9P P11C P11P P1C P1P P3C P3P P5C P5P P7C P7P Options PFM 0, 1 Clock SM, SPI0, SPI1 Pre. & SM Clock SPI0 I/O & F0SPI Clock SPI1 I/O & F1SPI Clock F2SPI Clock PWM 8, 9 Clock PWM 8, 9 Period PWM 10, 11 Clock PWM 10, 11 Period PWM 0, 1 Clock PWM 0, 1 Period PWM 2, 3 Clock PWM 2, 3 Period PWM 4, 5 Clock PWM 4, 5 Period PWM 6, 7 Clock PWM 6, 7 Period Table 31-1: HW Options Field Offs. 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E Mne. T0C T1C T2C T3C T4C CO00C CO01C RZPC DMAC CO1C C0C C1C DC LC AC Options Timer 0 Clock Timer 1 Clock Timer 2 Clock Timer 3 Clock Timer 4 Clock Clock Out 0: Mux0 Pre. & Clock Clock Out 0: Mux1 Clock Rotor Zero Position Detection Clock DMA Timer Clock Clock Out 1: Pre. & Clock CAPCOM Counter 0 Clock CAPCOM Counter 1 Clock DIGITbus Clock LCD Pre. & Clock AM Clock Micronas Feb. 10, 2005; 6251-579-1DS 209 CDC 32xxG-C Table 31-1: HW Options Field Offs. 0x20 f0 0x21 f1 0x22 f2 0x23 f3 0x24 f4 0x25 f5 0x26 f6 0x27 f7 0x28 f8 0x29 0x2A f10 0x2B f11 0x2C 0x2D 0x2E f14 0x2F f15 f16 UA0 UA1 UART0 I/O f12 UART1 I/O f13 PM Port Mux f9 f0 f1 f1/21 f1/22 f1/23 f1/24 f1/25 f1/26 f1/27 f1/28 f1/29 f1/210 f1/211 f1/212 f1/213 f1/214 f1/215 f1/216 VSS T0-OUT VSS fSM fSM/28 fCC0IN fCC1IN VSS f1/21 VSS f1/29 Mne. Options DATA SHEET Table 31-3: Clock option selection code Clock Option Number Clock Signal Selection Code xxx0.0000 xxx0.0001 xxx0.0010 xxx0.0011 xxx0.0100 xxx0.0101 xxx0.0110 xxx0.0111 xxx0.1000 xxx0.1001 xxx0.1010 xxx0.1011 xxx0.1100 xxx0.1101 xxx0.1110 xxx0.1111 xxx1.0000 xxx1.0001 xxx1.0010 xxx1.0011 xxx1.0100 xxx1.0101 xxx1.0110 xxx1.0111 xxx1.1000 xxx1.1001 ... xxx1.1100 xxx1.1101 ... xxx1.1111 31.3. HW Options Registers and Code The mapping of the HW options registers corresponds exactly to the HW options field in the section above. The order of the HW options registers description in this section does not correspond to the order of the HW options field. The emulator IC allow SW programming of the whole registers. Future mask ROM derivatives do not allow writing other clock option values than defined in the HW options field. The clock options may be programmed to values according to table 31-3 on page 210. Some of the clocks may be prescaled by a programmable value. Refer to table 31-2 for possible values. f17 f18 f19 f20 f21 f22 1) f23 f24 f25, 26, 27 f28 f29, 30 f31 Table 31-2: Clock prescaler PRE 1 x 0 1 0 0 1 1 direct 1/1.5 1/2.5 Prescale Value If the leading "x" in the clock sampling table are not used for the purpose of coding other options, they must be replaced by zeros. 1) Clock option f22 is only available if the stepper motor module has been enabled by the standby bit. 210 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 31.3.1. Timers P3C T0C 7 w x x PWM 2, 3 Clock 7 6 x x Timer 0 Clock 6 x x 5 x x 4 3 2 1 0 5 x x 4 3 2 1 0 w x x Clock Options f0 to f31 (all) 0x0 Res Clock Options f1 to f31 0x01 Res P3P T1C 7 w x x PWM 2, 3 Period 7 6 x x Timer 1 Clock 6 x x 5 x x 4 3 2 1 0 5 x x 4 3 2 1 0 w x x Clock Options f0 to f31 (all) 0x08 Res Clock Options f0 to f31 (all) 0x0 Res P5C T2C 7 w x x PWM 4, 5 Clock 7 6 x x Timer 2 Clock 6 x x 5 x x 4 3 2 1 0 5 x x 4 3 2 1 0 w x x Clock Options f0 to f31 (all) 0x0 Res Clock Options f0 to f31 (all) 0x0 Res P5P T3C 7 w x x PWM 4, 5 Period 7 6 x x Timer 3 Clock 6 x x 5 x x 4 3 2 1 0 5 x x 4 3 2 1 0 w x x Clock Options f0 to f31 (all) 0x08 Res Clock Options f0 to f31 (all) 0x0 Res P7C T4C 7 w x x PWM 6, 7 Clock 7 6 x x Timer 4 Clock 6 x x 5 x x 4 3 2 1 0 5 x x 4 3 2 1 0 w x x Clock Options f0 to f31 (all) 0x0 Res Clock Options f0 to f31 (all) 0x0 Res P7P PWM 6, 7 Period 7 6 x x 31.3.2. PWMs The high pulse width of the trigger period must be greater than the high pulse width of the clock the PWM is provided with. w 5 x x 4 3 2 1 0 x x Clock Options f0 to f31 (all) 0x08 Res P1C 7 w x x PWM 0, 1 Clock 6 x x P9C 2 1 0 w Res PWM 8, 9 Clock 7 x x 5 x x 4 3 6 x x 5 x x 4 3 2 1 0 Clock Options f0 to f31 (all) 0x0 Clock Options f0 to f31 (all) 0x0 Res P1P 7 w x x PWM 0, 1 Period 6 x x P9P 2 1 0 w Res PWM 8, 9 Period 7 x x 5 x x 4 3 6 x x 5 x x 4 3 2 1 0 Clock Options f0 to f31 (all) 0x08 Clock Options f0 to f31 (all) 0x08 Res Micronas Feb. 10, 2005; 6251-579-1DS 211 CDC 32xxG-C 31.3.7. Clock Out P11C 7 w x x DATA SHEET PWM 10, 11 Clock 6 x x 5 x x 4 3 2 1 0 CO00C 7 Res w x x Clock Out 0: Mux0 Pre. & Clock 6 PRE 0x0 Clock Options f0 to f31 (all) 0x0 5 4 3 2 1 0 Clock Options f0 to f31 (all) 0x11 Res P11P 7 w x x PWM 10, 11 Period 6 x x PRE 2 1 0 Prescaler (Table 31-2) 5 x x 4 3 Clock Options f0 to f31 (all) 0x08 Res CO01C 7 w x x Clock Out 0: Mux1 Clock 6 x x 5 x x 4 3 2 1 0 Clock Options f0 to f31 (all) 0x0 Res 31.3.3. CAPCOMs C0C 7 w x x CAPCOM Counter 0 Clock 6 x x RZPC 0 7 6 x x Rotor Zero Position Detection Clock 5 x x 5 x x 4 3 2 1 4 3 2 1 0 Clock Options f0 to f31 (all) w 0x0 Res x 0x0 Res x Clock Options f0 to f31 (all) C1C 7 w x x CAPCOM Counter 1 Clock 6 x x CO1C 0 7 6 PRE 0x0 Clock Out 1: Pre. & Clock 5 4 3 2 1 0 5 x x 4 3 2 1 Clock Options f0 to f31 (all) w 0x0 Res x 0x11 Res x Clock Options f0 to f31 (all) 31.3.4. DIGITbus DC 7 w x x PRE Prescaler (Table 31-2) DIGITbus Clock 6 x x 31.3.8. LCD 2 1 0 5 x x 4 3 LC Clock Options f0 to f31 (all) LCD Pre. & Clock 7 6 PRE 0x0 5 4 3 2 1 0 0x0 Res w x x Clock Options f0 to f31 (all) 0x03 Res 31.3.5. DMA PRE DMAC 7 w x x Prescaler (Table 31-2) DMA Timer Clock 6 x x 5 x x 4 3 2 1 0 31.3.9. Stepper Motor and SPIs SMC SM, SPI0, SPI1 Pre. & SM Clock 6 PRE 0x0 Clock Options f0 to f31 (all) 0x0 Res 7 5 4 3 2 1 0 31.3.6. PFM PF0C 7 w x x w x x Clock Options f0 to f31 (all) 0x0 Res PFM 0, 1 Clock 6 x x PRE 2 1 0 Prescaler (Table 31-2) 5 x x 4 3 Clock Options f0 to f31 (all) 0x0 Res The field PRE of register SMC defines the SPI0 and SPI1 prescaler setting too. 212 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C U15 w1: w0: 1 0 SP0C 7 6 SPI0 I/O & F0SPI Clock 5 x x U-Port 1.5 Output Select CO1. CO0Q. CAPCOM4-IN Select Input from P0.0. Input from U5.3. CAPCOM0, 1, 2-IN and DIGIT-IN Select Table 31-4. 4 3 2 w SPI0OUT SPI0IN 0 0 Clock Options f0 to f31 (all) 0x0 Res CC4I w1: w0: CACO w1/0: SPI0OUT w1: w0: SPI0IN w1: w0: SPI0 Data Output Inverter Inverted. Direct. SPI0 Data Input Inverter Inverted. Direct. Table 31-4: PM.CACO Usage Signal CAPCOM0-IN CAPCOM1-IN PM.CACO = 0 U3.2 U3.1 U3.0 U2.4 U-Port 0.6 Output Select CC3-OUT. T4-OUT. U-Port 2.0 Output Select Table 31-5. PM.CACO = 1 U4.1 U2.4 U2.2 U2.6 The clock is prescaled by SMC.PRE. SP1C 7 6 SPI1 I/O & F1SPI Clock 5 x x CAPCOM2-IN 1 0 4 3 2 DIGIT-IN U06 w1: w0: U20 w1/0: w SPI1OUT SPI1IN 0 0 Clock Options f0 to f31 (all) 0x0 Res SPI1OUT w1: w0: SPI1IN w1: w0: SPI1 Data Output Inverter Inverted. Direct. SPI1 Data Input Inverter Inverted. Direct. Table 31-5: PM.U20 Usage Signal CAN0-TX PM.U20 = 0 U2.0 and U4.2 U2.1 not usable not usable H-Port 7 Output Select PWM9, 8, 6, 4. SME. H-Port 0 Output Select PWM7, 5, 3, 1. SMG. Port Interrupt Select Input from P1.2 to P1.7. Input from U1.7, U1.6, U1.5, U0.7, U0.5, U0.4. PM.U20 = 1 U4.2 U4.3 U2.0 U2.1 The clock is prescaled by SMC.PRE. SP2C 7 w x x F2SPI Clock 6 x x CAN0-RX 3 2 1 0 5 x x 4 SCL0 SDA0 Res Clock Options f0 to f31 (all) 0x0 The clock is prescaled by SMC.PRE. H7 w1: w0: H0 w1: w0: 31.3.10. Audio Module AC 7 w x x AM Clock 6 x x 5 x x 4 3 2 1 0 Clock Options f0 to f31 (all) 0x0 Res PINT w1: w0: 31.3.12. UARTs UA0 7 6 U0RX 0 31.3.11. Port Multiplexers PM 7 w U15 0 UART0 I/O 5 x x 4 x x 3 x x 2 x x 1 x x 0 x x Res Port Mux w U0TX 0 CC4I 0 CACO 0 U20 1 U06 0 H7 0 H0 0 PINT 0 Res 6 5 4 3 2 1 0 U0TX w1: w0: UART0 Tx Inversion Select Inverted. Direct. Micronas Feb. 10, 2005; 6251-579-1DS 213 CDC 32xxG-C U0RX w1: w0: UART0 Rx Inversion Select Inverted. Direct. DATA SHEET UA1 7 w U1TX 0 UART1 I/O 6 U1RX 0 5 x x 4 x x 3 x x 2 x x 1 x x 0 x x Res U1TX w1: w0: U1RX w1: w0: UART1 Tx Inversion Select Inverted. Direct. UART1 Rx Inversion Select Inverted. Direct. 214 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 32. Register Cross Reference Table 32.1. 8-Bit I/O Region Table 32-1: Base address 0x00F80000 Offs. 0xFFC 0x800 0x7FC 0x600 0x5FC 0x400 0x3FC 0x200 0x1FC 0x000 Byte Address 3 Remarks 2 1 0 4 CAN reserved CAN 3 CAN 2 CAN 1 CAN 0 Module CAN RAM Micronas Feb. 10, 2005; 6251-579-1DS 215 CDC 32xxG-C DATA SHEET Table 32-2: Base address 0x00F81000 Offs. 0x1FC 0x100 0x0FC 0x0D4 0x0D0 0x0CC 0x0C8 0x0C4 0x0C0 0x0BC 0x094 0x090 0x08C 0x088 0x084 0x080 0x07C 0x054 0x050 0x04C 0x048 0x044 0x040 0x03C 0x014 0x010 0x00C 0x008 0x004 0x000 Byte Address 3 Remarks 2 1 0 4 CAN reserved CAN3 CTIM TEC BT2 STR Module CAN register ESM ICR IDM IDX REC BT3 ESTR OCR BT1 CTR CAN2 ESM ICR IDM IDX REC BT3 ESTR CTIM TEC BT2 STR OCR BT1 CTR CAN1 ESM ICR IDM IDX REC BT3 ESTR CTIM TEC BT2 STR OCR BT1 CTR CAN0 ESM ICR IDM IDX REC BT3 ESTR CTIM TEC BT2 STR OCR BT1 CTR 216 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Table 32-3: Base address 0x00F90000 (formerly 1F00) Offs. 0x0FC 0x0F8 0x0F4 0x0F0 0x0EC 0x0B0 0x0AC 0x0A8 0x0A4 0x0A0 0x09C 0x080 0x07C 0x078 0x074 0x070 0x06C 0x068 0x064 0x060 0x05C 0x058 0x054 0x050 0x04C 0x048 0x044 0x040 0x03C 0x030 0x02C 0x028 0x024 0x020 0x01C 0x018 0x014 0x010 0x00C 0x008 0x004 0x000 Byte Address 3 TST2 TST5 DGRTMA DGRTMD Remarks 2 TST1 DGTD DGS0 1 TST3 TSTAD3 DGS1TA DGC1 0 TST4 TSTAD2 DGTL DGC0 64 byte ANAA AD0 UA0IM UA0D 32 byte CCC0H CC3I CC2I CC1I CC0I CCC0L CC3M CC2M CC1M CC0M CAPCOM0 CC3 CC2 CC1 CC0 8 byte Core Logic Stepper Motor Module VDO Timer Timer0 CCC1H CC5I CC4I CCC1L CC5M CC4M CAPCOM1 CC5 CC4 16 byte Audio Module Port Interrupt 8 byte UA1IF UA1BR0 SPI1D UA1CA UA1C SPI0M UA1IM UA1D CO0SEL SPI0D UART1 Core Logic SPI Core Logic ADC UART0 Module Test DIGITBus UA0BR1 UA0IF UA0BR0 AD1 UA0CA UA0C CC3H CC2H CC1H CC0H CC3L CC2L CC1L CC0L SMVMUX SMVSIN TIM4 TIM0H CC5H CC4H DBG SMVCMP SMVC TIM3 TIM0L CC5L CC4L TIM2 CSW1 SMVCOS TIM1 AMDEC IRPM1 AMF IRPM0 AMAS AMPRE UA1BR1 SPI1M SR1 SR0 ANAU CSW0 Micronas Feb. 10, 2005; 6251-579-1DS 217 CDC 32xxG-C DATA SHEET Table 32-4: Base address 0x00F90100 (formerly 1E00) Offs. 0x0FC 0x0F0 0x0EC 0x0E8 0x0E4 0x0E0 0x0DC 0x0D8 0x0D4 0x0D0 0x0CC 0x0C8 0x0C4 0x0C0 0x0BC 0x060 0x05C 0x058 0x054 0x050 0x04C 0x048 0x044 0x040 0x03C 0x020 0x01C 0x018 0x014 0x010 0x00C 0x008 0x004 0x000 Byte Address 3 Remarks 2 1 0 16 byte UA1 PM UA0 Module HW Options P7P P3P P11P SP2C PF0C C1C RZPC T3C P7C P3C P11C SP1C AC C0C CO01C T2C P5P P1P P9P SP0C LC CO1C CO00C T1C P5C P1C P9C SMC DC DMAC T4C T0C 96 byte PFM PFM1 PFM0 PWMC PWM11 PWM7 PWM3 PWM PWM10 PWM6 PWM2 PWM9 PWM5 PWM1 PWM8 PWM4 PWM0 32 byte I2C1 I2C I2CM1 I2CRS1 I2CWD11 I2CM0 I2CRS0 I2CWD10 I2CRD1 I2CWD01 I2CWP11 I2CWS11 I2CWP01 I2CWS01 I2C0 I2CRD0 I2CWD00 I2CWP10 I2CWS10 I2CWP00 I2CWS00 218 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Table 32-5: Base address 0x00F90400 Offs. 0x0FC 0x0F8 0x0F4 0x0F0 0x0EC 0x0E8 0x0E4 0x0E0 0x0DC 0x0D8 0x0D4 0x0D0 0x0CC 0x0C8 0x0C4 0x0C0 0x0BC 0x0B8 0x0B4 0x0B0 0x0AC 0x090 0x084 0x080 0x074 0x070 0x064 0x060 0x054 0x050 0x044 0x040 0x034 0x030 0x024 0x020 0x014 0x010 0x004 0x000 Byte Address 3 HxLVL HxLVL HxLVL HxLVL HxLVL HxLVL HxLVL HxLVL P2LVL P1LVL P0LVL Remarks 2 HxNS HxNS HxNS HxNS HxNS HxNS HxNS HxNS 1 HxTRI HxTRI HxTRI HxTRI HxTRI HxTRI HxTRI HxTRI P2IE P1IE P0IE 0 HxPIN HxD HxPIN HxD HxPIN HxD HxPIN HxD HxPIN HxD HxPIN HxD HxPIN HxD HxPIN HxD P2PIN P1PIN P0PIN H-Port7 H-Port6 H-Port5 H-Port4 H-Port3 H-Port2 H-Port1 H-Port0 P-Ports P-Port 2 P-Port1 P-Port 0 reserved U-Port 8 U-Port 7 U-Port 6 U-Port 5 U-Port 4 U-Port 3 U-Port 2 U-Port 1 U-Port 0 Module H-Ports U-Ports UxMODE UxDPM UxMODE UxDPM UxMODE UxDPM UxMODE UxDPM UxMODE UxDPM UxMODE UxDPM UxMODE UxDPM UxMODE UxDPM UxMODE UxDPM UxPIN UxNS UxPIN UxNS UxPIN UxNS UxPIN UxNS UxPIN UxNS UxPIN UxNS UxPIN UxNS UxPIN UxNS UxPIN UxNS UxLVL UxTRI UxLVL UxTRI UxLVL UxTRI UxLVL UxTRI UxLVL UxTRI UxLVL UxTRI UxLVL UxTRI UxLVL UxTRI UxLVL UxTRI UxSLOW UxD UxSLOW UxD UxSLOW UxD UxSLOW UxD UxSLOW UxD UxSLOW UxD UxSLOW UxD UxSLOW UxD UxSLOW UxD Micronas Feb. 10, 2005; 6251-579-1DS 219 CDC 32xxG-C Table 32-6: Base address 0x00F90500 Offs. 0x0FC 0x080 0x07C 0x078 0x074 0x070 0x06C 0x068 0x064 0x060 0x05C 0x058 0x054 0x050 0x04C 0x048 0x044 0x040 0x03C 0x030 0x02C 0x028 0x024 0x020 0x01C 0x014 0x010 0x00C 0x008 0x004 0x000 Byte Address 3 Remarks 2 1 0 128 Bytes SMX POL RTCC OSC WSC WPM8 WPM0 Polling RTC DATA SHEET Module reserved Power Saving Wake Ports mode RTC WPM6 RTC SSC SSR WPM4 WPM2 WUS Wake-up source reserved GC GD GBus MDL MFPLR WSR IOC ERMC PLLC Memory Ctrl. DLM Clock, PLL, ERM Core Logic reserved ULCDLD LCD Patch PER PDR PAR 220 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 32.2. 32-Bit I/O Region Table 32-7: Base address 0x00FFFD00 Offs. 0x0FC 0x004 0x000 Byte Address 3 Remarks 2 1 0 252 bytes reserved CR Control Register Module Core Logic Table 32-8: Base address 0x00FFFE00 Offs. 0x0FC 0x020 0x018 0x010 0x008 0x004 0x000 Byte Address 3 Remarks 2 1 0 rsvd Channel 4 to 31 DC3M DC2M DC1M DST DVB Channel 3 Channel 2 Channel 1 Control Module DMA Table 32-9: Base address 0x00FFFF00 Offs. 0x0FC 0x0F4 0x0F0 0x0EC 0x0C8 0x0C4 0x0C0 0x0BC 0x040 0x03C 0x028 0x024 : 0x004 0x000 Byte Address 3 Remarks 2 1 0 12 bytes reserved CRF PRF FIQ registers 40 bytes reserved IRQ registers PEPRIO AFP CRI 128 bytes reserved Interrupt source nodes ISN39 : ISN7 ISN3 ISN38 : ISN6 ISN2 ISN37 : ISN5 ISN1 ISN36 : ISN4 ISN0 Module IRQ and FIQ Interrupt Controller VTB PESRC Micronas Feb. 10, 2005; 6251-579-1DS 221 CDC 32xxG-C DATA SHEET 222 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 33. Register Quick Reference The I/O area is organized in little endian format, thus the LSB, independent of the flag CR.ENDIAN setting, is always stored at the low address. Table 33-1: Analog section (base addr. 0xF90000) Mnemonic Register Name Offs. 7 AD0 ADC Register 0 0x0A8 6 Register Configuration 5 4 3 2 1 0 15.7. Section r w EOC TSAMP 0 x x REF x x TEST AN1 AN0 CHANNEL 0 0 0 0 0 Res 0 0 AD1 ADC Register 1 0x0A9 r w AN9 x AN8 x AN7 x AN6 x AN5 x AN4 x AN3 x AN2 BUF 0 Res ANAA Analog AVDD Register 0x0AC r/w EP06 0 P06 WAIT x x x x BVE 0 Res Table 33-2: Analog input ports (base addr. 0xF90400) Mnemonic Register Name Offs. 7 P0PIN P1PIN P2PIN P0IE Port x Input Enable Register Port x Pin Register 0x0B0 0x0B4 0x0B8 0x0B1 r/w I7 0 I Register Configuration 6 5 4 3 2 1 0 Section r P7 1 P6 1 P5 1 P4 1 P3 1 P2 1 P1 1 P0 1 Res 14.1. I6 0 I5 0 I4 0 I3 0 I2 0 I1 0 I0 0 Res P1IE 0x0B5 r/w I7 0 I6 0 I5 0 I4 0 I3 0 I2 0 I1 1 I0 1 Res I P2IE 0x0B9 r/w x x x x x x I1 0 I0 0 Res I P0LVL P1LVL P2LVL Port x Level Register 0x0B3 0x0B7 0x0BB r/w A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 Res Micronas Feb. 10, 2005; 6251-579-1DS 223 CDC 32xxG-C DATA SHEET Table 33-3: Audio module (base addr. 0xF90000) Mnemonic Register Name Offs. 7 AMPRE Audio Module Prescaler 0x02C 6 Register Configuration 5 4 3 2 1 0 30.2. 1 1 1 Res Section w 1 1 1 Prescale Value 1 1 AMAS Audio Module Amplitude & Status Register 0x02D w r AMA 0 x x x x Initial Amplitude x x x x x x x x x x Res AMF Audio Module Frequency Register 0x02E w x 0 0 Sound Frequency 0 0 0 0 0 Res AMDEC Audio Module Decrement Register 0x02F w AMMCA 0 x - x - x - x 0 GDF 0 0 Res 224 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Table 33-4: Capture-compare-unit 0 (base addr. 0xF90000) Mnemonic Register Name Offs. 7 CC0M CC1M CC2M CC3M CC0I CC1I CC2I CC3I CC0L CC1L CC2L CC3L CC0H CC1H CC2H CC3H CCC0L CAPCOM Counter 0 low byte CAPCOM 0 Capture/ Compare Register high byte CAPCOM 0 Capture/ Compare Register low byte CAPCOM 0 Interrupt Register CAPCOM 0 Mode Register 0x06C 0x070 0x074 0x078 0x06D 0x071 0x075 0x079 0x06E 0x072 0x076 0x07A 0x06F 0x073 0x077 0x07B 0x07C r 0 0 Read low byte and lock CCC 0 0 0 0 0 0 Res r w 1 Read high byte of capture register and unlock it. Write high byte of compare register and unlock it. 1 1 1 1 1 1 1 Res r w 1 Read low byte of capture register and lock it. Write low byte of compare register and lock it. 1 1 1 1 1 1 1 Res r/w CAP 0 CMP 0 OFL 0 LAC 0 RCR 0 x 0 x 0 x 0 Res Register Configuration 6 5 4 3 2 1 0 Section r/w MCAP 0 MCMP 0 MOFL 0 FOL 0 0 OAM 0 0 IAM 0 Res 19.2. CCC0H CAPCOM Counter 0 high byte 0x07D r 0 0 Read high byte and unlock CCC 0 0 0 0 0 0 Res Micronas Feb. 10, 2005; 6251-579-1DS 225 CDC 32xxG-C DATA SHEET Table 33-5: Capture-compare-unit 1 (base addr. 0xF90000) Mnemonic Register Name Offs. 7 CC4M CC5M CC4I CC5I CC4L CC5L CAPCOM Capture/ Compare Register low byte CAPCOM Interrupt Register CAPCOM Mode Register 0x040 0x044 0x041 0x045 0x042 0x046 6 Register Configuration 5 4 3 2 1 0 19.2. 0 Res Section r/w MCAP 0 MCMP 0 MOFL 0 FOL 0 0 OAM 0 0 IAM r/w CAP 0 CMP 0 OFL 0 LAC 0 RCR 0 x 0 x 0 x 0 Res r w 1 Read low byte of capture register and lock it. Write low byte of compare register and lock it. 1 1 1 1 1 1 1 Res CC4H CC5H CAPCOM Capture/ Compare Register high byte 0x043 0x047 r w 1 Read high byte of capture register and unlock it. Write high byte of compare register and unlock it. 1 1 1 1 1 1 1 Res CCC1L CAPCOM Counter 1 low byte 0x048 r 0 0 Read low byte and lock CCC 0 0 0 0 0 0 Res CCC1H CAPCOM Counter 1 high byte 0x049 r 0 0 Read high byte and unlock CCC 0 0 0 0 0 0 Res 226 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Table 33-6: Controller area network registers (base addr. 0xF81000) Mnemonic Register Name Offs. 7 CAN0CTR CAN1CTR CAN2CTR CAN3CTR CAN0STR CAN1STR CAN2STR CAN3STR CAN0ESTR CAN1ESTR CAN2ESTR CAN3ESTR CAN0IDX CAN1IDX CAN2IDX CAN3IDX CAN0IDM CAN1IDM CAN2IDM CAN3IDM Identifier Mask Register Interrupt Index Register Error Status Register Status Register Control Register 0x000 0x040 0x080 0x0C0 0x001 0x041 0x081 0x0C1 0x002 0x042 0x082 0x0C2 0x003 0x043 0x083 0x0C3 0x004 0x044 0x084 0x0C4 r/w r/w r/w r/w 0 0 Identifier Mask Bits 4 to 0 x x x 3 2 1 0 0 0 Res r/w 1 1 1 Interrupt Index 1 1 1 1 1 Res r/w GDM 0 CTOV 0 ECNT 0 BIT 0 STF 0 CRC 0 FRM 0 ACK 0 Res r HACK 1 BOFF 0 EPAS 0 ERS 0 rsvd x rsvd x rsvd x rsvd x Res Register Configuration 6 5 4 3 2 1 0 Section r/w HLT 1 SLP 0 GRSC 0 EIE 0 GRIE 0 GTIE 0 BOST 0 rsvd x Res 27.2. Identifier Mask Bits 12 to 5 Identifier Mask Bits 20 to 13 Identifier Mask Bits 28 to 21 0 0 0 0 CAN0BT1 CAN1BT1 CAN2BT1 CAN3BT1 CAN0BT2 CAN1BT2 CAN2BT2 CAN3BT2 Bit Timing Register 1 0x008 0x048 0x088 0x0C8 r/w MSAM 0 SYN 0 0 0 0 BPR 0 0 0 Res Bit Timing Register 2 0x009 0x049 0x089 0x0C9 r/w rsvd 0 0 TSEG2 0 0 0 0 TSEG1 0 0 Res Micronas Feb. 10, 2005; 6251-579-1DS 227 CDC 32xxG-C Table 33-6: Controller area network registers (base addr. 0xF81000) Mnemonic Register Name Offs. 7 CAN0BT3 CAN1BT3 CAN2BT3 CAN3BT3 CAN0ICR CAN1ICR CAN2ICR CAN3ICR CAN0OCR CAN1OCR CAN2OCR CAN3OCR CAN0TEC CAN1TEC CAN2TEC CAN3TEC CAN0REC CAN1REC CAN2REC CAN3REC CAN0ESM CAN1ESM CAN2ESM CAN3ESM CAN0CTIM CAN1CTIM CAN2CTIM CAN3CTIM Capture Timer Error Status Mask Register Receive Error Counter Transmit Error Counter Output Control Register Input Control Register Bit Timing Register 3 0x00A 0x04A 0x08A 0x0CA 0x00B 0x04B 0x08B 0x0CB 0x00C 0x04C 0x08C 0x0CC 0x00D 0x04D 0x08D 0x0CD 0x00E 0x04E 0x08E 0x0CE 0x00F 0x04F 0x08F 0x0CF 0x010 0x050 0x090 0x0D0 r r 0 0 0 Timer Bit 15 to 8 Timer Bit 7 to 0 0 0 0 0 0 1 0 Res r/w EGDM 1 ECTV 1 EECT 1 EBIT 1 ESTF 1 ECRC 1 EFRM 1 EACK 1 Res r x x 0 0 Counter Bit 6 to 0 0 0 0 0 0 Res r 0 0 0 Counter Bit 7 to 0 0 0 0 0 0 Res r/w rsvd x rsvd x rsvd x rsvd x rsvd x rsvd x rsvd x ITX 0 Res r/w rsvd x rsvd x rsvd x rsvd x rsvd x XREF x REF1 0 REF0 0 Res DATA SHEET Register Configuration 6 5 4 3 2 1 0 Section r/w rsvd x rsvd x rsvd x rsvd x rsvd x 0 SJW 0 0 Res 27.2. 228 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Table 33-7: Core logic 32-bit (base addr. 0xFFFD00) Mnemonic Register Name Offs. 7 CR Control Register 0x000 6 Register Configuration 5 4 3 2 1 0 6.1. Section r/w x x x x TETM MAP x x EB1 x x EBW IBOOT x TSTTOG EASY IROM x EWE x PSA 3 2 1 0 Res r/w STPCLK RESLNG r/w r/w EB2 JTAG TFT ENDIAN MFM IRAM ICPU Value of memory location 0x20 to 0x23 Table 33-8: Core Logic 8-bit (base addr. 0xF90000) Mnemonic Register Name Offs. 7 CSW0 Clock, Supply and Watchdog Register 0 0x000 6 Register Configuration 5 4 3 2 1 0 6. Res Section w FHR 0 x x x x x x x x x x x x CMA 1 ANAU Analog UVDD Register 0x004 r/w EAL 0 x 0 LS 0 LE 0 x - FVE 0 VE 0 Res SR0 Standby Register 0 0x008 r/w r/w r/w r/w I2C1 TIM2 LCD SM I2C0 TIM3 x x x TIM4 PSLW x x UART1 UART0 x x x ADC SPI1 CAN3 DGB x CAN0 CAN2 CCC1 TIM1 CCC0 CAN1 x XTAL SPI0 3 2 1 0 Res 0x00000100 SR1 Standby Register 1 0x00C r/w r/w r/w r/w x x PFM1 IRQ x x PFM0 FIQ x x PWM11 x x x PWM9 x x x PWM7 x x x PWM5 x x PWM3 CPUM x x PWM1 3 2 1 0 Res 0x00000001 CO0SEL Clock Out 0 Selection 0x014 w x x x x x x x x x x x x CO01 0 CO00 0 Res CSW1 Clock, Supply and Watchdog Register 1 0x060 w 1 r TST 1 IDLE 0 Watchdog Time and Trigger Value 1 WKST 0 1 FHR 0 1 CLM 0 1 PIN 0 1 POR 0 1 WDRES 0 Res Res Micronas Feb. 10, 2005; 6251-579-1DS 229 CDC 32xxG-C DATA SHEET Table 33-9: Core logic 8-bit (base addr. 0xF90500) Mnemonic Register Name Offs. 7 PLLC PLL Control 0x020 6 Register Configuration 5 4 3 2 1 0 6. 0 0 Res Section r/w ACT x LCK x PLLM x x x 0 0 PMF ERMC ERM Control 0x024 r/w r/w r/w r/w x EOM INPH x x x x x x TSEL x x TOL SUP 0x00000000 x x 3 2 1 0 Res IOC I/O Control 0x028 w x x x x x x x x x x 0 IOP 0 0 Res WSR Wait State Register 0x02C w NWS 0x00 SWS Res MFPLR Multi Function Port Lock Register 0x030 r/w x x x x x x x MFPL x x x x x x x 11) Res MDL Memory Delay 0x03C w w x x x x x x x x 0x0000 MDDL MCDL 1 0 Res 34.2. 230 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Table 33-10: DIGITbus (base addr. 0xF90000) Mnemonic Register Name Offs. 7 DGC0 Control Register 0 0x0F0 6 Register Configuration 5 4 3 2 1 0 29.3. 0 Res Section r/w RUN 0 GBC 0 ACT 0 RXO 0 X x 0 PSC 2 to 0 0 DGC1 Control Register 1 0x0F1 r/w INTE 0 ENEM 0 ENOF 0 x x 0 0 PHASE 0 0 Res DGS0 Status Register 0 0x0F2 w r x RDL x x NEM 0 x NOF 1 TGV PV ERR x ARB 0 0 0 x 0 Res DGRTMD Rx Length & Tx More Data Register 0x0F3 w r RDL 0 NEM 0 FTYP x Transmit More Data EOFLD x x x x LEN2 to 0 x x Res DGTL Tx Length Register 0x0F4 w x x FLUSH 0 EMPTY 1 x x x x x x x x x x x x 0 x x LEN2 to 0 0 x x 0 x x Res Res r BUSY 0 DGS1TA Status 1 & Tx Address Register 0x0F5 w r 0 STATE 1 0 Transmit Address PW5 to 0 0 0 0 0 0 Res DGTD Tx Data Register 0x0F6 w x x x Transmit Data x x x x x Res DGRTMA Rx Field & Tx More Address Register 0x0F7 w r x x x Transmit More Address Receive Field x x x x x Res Micronas Feb. 10, 2005; 6251-579-1DS 231 CDC 32xxG-C DATA SHEET Table 33-11: DMA (base addr. 0xFFFE00) Mnemonic Register Name Offs. 7 DVB DMA Vector Base 0x000 6 Register Configuration 5 4 3 2 1 0 22.2. Section r/w r/w r/w r/w 0 0 0 0 0 0 0 0 3 2 1 A23 to A16 A15 to A8 A7 0 0 0 0x0000 0 0 0 0 0 Res DST DMA Status 0x004 r/w DE x x 0x00 SRC 0 Res DC1M DC2M DC3M DMA Channel x Mode 0x008 0x010 0x018 r/w r/w P EN x DMAT x x BYP 0x0000 DIR TRIG MAS 1 0 Res Table 33-12: FIQ interrupt logic (base addr. 0xFFFF00) Mnemonic Register Name Offs. 7 PRF Pending Register FIQ 0x0F0 6 Register Configuration 5 4 3 2 1 0 12.2. Res Section r/w x x x x x x x x x x x x x x P 0 CRF Control Register FIQ 0x0F1 r/w GE 0 x x x x x x 0 0 SEL 0 0 Res Table 33-13: Graphic bus interface (base addr. 0xF90500) Mnemonic Register Name Offs. 7 GD Graphic Bus Data Register 0x040 6 Register Configuration 5 4 3 2 1 0 23.2. Section r/w Data 0x00 0 Res GC Graphic Bus Control Register 0x044 r/w TIM 0x00 E BSY SEQ DTA 0 Res 232 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Table 33-14: Hardware options registers (base addr. 0xF90100) Mnemonic Register Name Offs. 7 T0C Timer 0 Clock 0x0C0 6 Register Configuration 5 4 3 2 1 0 31.3. Res Section w x x x x x x Clock Options f1 to f31 0x01 T1C T2C T3C T4C CO00C Timer 1 to 4 Clock 0x0C1 0x0C2 0x0C3 0x0C4 w x x x x x x Clock Options f0 to f31 (all) 0x0 Res Clock Out0: Mux0 Pre. & Clock 0x0C5 w x x PRE 0x0 Clock Options f0 to f31 (all) 0x11 Res CO01C Clock Out0: Mux1 to Mux3 Clock 0x0C6 w x x x x x x Clock Options f0 to f31 (all) 0x0 Res RZPC Rotor Zero Position Detection Clock 0x0C7 w x x x x x x Clock Options f0 to f31 (all) 0x0 Res DMAC DMA Timer Clock 0x0C8 w x x x x x x Clock Options f0 to f31 (all) 0x0 Res CO1C Clock Out1: Pre. & Clock 0x0C9 w x x PRE 0x0 Clock Options f0 to f31 (all) 0x11 Res C0C C1C DC LC CAPCOM Counter Clocks DIGITbus Clock LCD Pre. & Clock 0x0CA 0x0CB 0x0CC 0x0CD w x x x x x x Clock Options f0 to f31 (all) 0x0 Res w x x PRE 0x0 Clock Options f0 to f31 (all) 0x03 Res AC AM Clock 0x0CE w x x x x x x Clock Options f0 to f31 (all) 0x0 Res PF0C PFM 0 Clock 0x0CF w x x x x x x Clock Options f0 to f31 (all) 0x0 Res Micronas Feb. 10, 2005; 6251-579-1DS 233 CDC 32xxG-C Table 33-14: Hardware options registers (base addr. 0xF90100) Mnemonic Register Name Offs. 7 SMC SM, SPI0, SPI1 Pre. & SM Clock 0x0D0 6 Register Configuration 5 4 3 2 1 0 DATA SHEET Section w x x PRE 0x0 Clock Options f0 to f31 (all) 0x0 Res 31.3. SP0C SPI0 I/O & F0SPI Clock 0x0D1 w SPI0OUT SPI0IN 0 0 x x Clock Options f0 to f31 (all) 0x0 Res SP1C SPI1 I/O & F1SPI Clock 0x0D2 w SPI1OUT SPI1IN 0 0 x x Clock Options f0 to f31 (all) 0x0 Res SP2C F2SPI Clock 0x0D3 w x x x x x x Clock Options f0 to f31 (all) 0x0 Res P9C P11C P1C P3C P5C P7C P9P P11P P1P P3P P5P P7P PM PWM Clock 0x0D4 0x0D6 0x0D8 0x0DA 0x0DC 0x0DE w x x x x x x Clock Options f0 to f31 (all) 0x0 Res PWM Period 0x0D5 0x0D7 0x0D9 0x0DB 0x0DD 0x0DF w x x x x x x Clock Options f0 to f31 (all) 0x08 Res Port Multiplexer 0x0E9 w U15 0 CC4I 0 CACO 0 U20 1 U06 0 H7 0 H0 0 PINT 0 Res UA0 UARTs 0x0EC w U0TX 0 U0RX 0 x x x x x x x x x x x x Res UA1 0x0ED w U1TX 0 U1RX 0 x x x x x x x x x x x x Res 234 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Table 33-15: High-current ports (base addr. 0xF90400) Mnemonic Register Name Offs. 7 H0D H1D H2D H3D H4D H5D H6D H7D H0TRI H1TRI H2TRI H3TRI H4TRI H5TRI H6TRI H7TRI H0NS H1NS H2NS H3NS H4NS H5NS H6NS H7NS High Current Port Normal/Special Register High Current Port Tristate Register High Current Port Data Register 0x0C0 0x0C8 0x0D0 0x0D8 0x0E0 0x0E8 0x0F0 0x0F8 0x0C1 0x0C9 0x0D1 0x0D9 0x0E1 0x0E9 0x0F1 0x0F9 0x0C2 0x0CA 0x0D2 0x0DA 0x0E2 0x0EA 0x0F2 0x0FA r/w x x x x x x x x S3 0 S2 0 S1 0 S0 0 Res r/w x x x x x x x x T3 0 T2 0 T1 0 T0 0 Res Register Configuration 6 5 4 3 2 1 0 Section r/w x x x x x x x x D3 0 D2 0 D1 0 D0 0 Res 14.5. Micronas Feb. 10, 2005; 6251-579-1DS 235 CDC 32xxG-C Table 33-15: High-current ports (base addr. 0xF90400) Mnemonic Register Name Offs. 7 H0LVL H1LVL H2LVL H3LVL H4LVL H5LVL H6LVL H7LVL H0PIN H1PIN H2PIN H3PIN H4PIN H5PIN H6PIN H7PIN High Current Port Pin Register High Current Port Level Register 0x0C3 0x0CB 0x0D3 0x0DB 0x0E3 0x0EB 0x0F3 0x0FB 0x0C4 0x0CC 0x0D4 0x0DC 0x0E4 0x0EC 0x0F4 0x0FC r x x x x x x x x P3 0 P2 0 P1 0 P0 0 Res DATA SHEET Register Configuration 6 5 4 3 2 1 0 Section r/w x x x x x x x x A3 0 A2 0 A1 0 A0 0 Res 14.5. 236 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Table 33-16: I2C-bus master interfaces (base addr. 0xF90100) Mnemonic Register Name Offs. 7 I2CWS00 I2CWS01 I2CWS10 I2CWS11 I2CWD00 I2CWD01 I2CWD10 I2CWD11 I2CWP00 I2CWP01 I2CWP10 I2CWP11 I2CRD0 I2CRD1 I2CRS0 I2CRS1 I2CM0 I2CM1 I2C Mode Register I2C Read Status Register I2C Read Data Register I2C Write Stop Register 1 I2C Write Stop Register 0 I2C Write Data Register 1 I2C Write Data Register 0 I2C Write Start Register 1 I2C Write Start Register 0 0x000 0x010 0x001 0x011 0x002 0x012 0x003 0x013 0x004 0x014 0x005 0x015 0x006 0x016 0x007 0x017 0x00B 0x01B 6 Register Configuration 5 4 3 2 1 0 26.2. Res Section w I2C Address 0x00 w I2C Address 0x00 Res w I2C Data 0x00 Res w I2C Data 0x00 Res w I2C Data 0x00 Res w I2C Data 0x00 Res r I2C Data 0x00 Res r x 0 OACK 0 AACK 0 DACK 0 BUSY 0 WFH 0 RFE 0 x 0 Res w DGL 1 SPEED 0x02 Res Micronas Feb. 10, 2005; 6251-579-1DS 237 CDC 32xxG-C DATA SHEET Table 33-17: Interrupt controller unit (base addr. 0xFFFF00) Mnemonic Register Name Offs. 7 ISN0 : ISN39 CRI Interrupt Source Node Register 0 : Interrupt Source Node Register 39 Control Register IRQ 0x000 : 0x027 0x0C0 6 Register Configuration 5 4 3 2 1 0 11.3. 0 0 Res Section r/w M 0 P x E 0 x x 0 0 PRIO r/w GE 0 TE 0 x x x x x x x x x x x x Res AFP Actual and Forced Priority Register 0x0C1 r/w 0 0 APRIO 0 0 0 0 FPRIO 0 0 Res PEPRIO Priority Encoder Priority output 0x0C2 r x x x x x x x x 0 0 Priority 0 0 Res PESRC Priority Encoder Source output 0x0C3 r x x x x 0 0 0 Source 0 0 0 Res VTB Vector Table Base 0x0C4 r/w r/w r/w r/w 0 0 0 0 0 0 0 0 3 2 Address bit 23 to 16 Address bit 15 to 9 0 0 0 0 0 0 0 0 0 1 0 Res 0x00000000 Table 33-18: JTAG (base addr. 0xF90000) Mnemonic Register Name Offs. 7 DBG Debug Register 0x061 6 Register Configuration 5 4 3 2 1 0 8.2. Section w x x x x x x x DISA 0 Res 0x01 (after UVDD power-up) 238 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Table 33-19: LCD (base addr. 0xF90500) Mnemonic Register Name Offs. 7 ULCDLD Universal Port LCD Load Register 0x010 6 Register Configuration 5 4 3 2 1 0 21.2. Res Section w LCDSLV 0 x 0 x 0 x 0 x 0 x 0 x 0 x 0 Table 33-20: Patch module (base addr. 0xF90500) Mnemonic Register Name Offs. 7 PAR Patch Address Register 0x000 6 Register Configuration 5 4 3 2 1 0 10.2. Section w w w w x x x x x x A22 to A16 x x x 3 2 1 A15 to A8 A7 to A2 0x00FFFFFF x x 0 Res PDR Patch Data Register 0x004 w w w w D31 to D24 D23 to D16 D15 to D8 D7 to D0 0x00000000 3 2 1 0 Res PER Patch Enable Register 0x008 w w w w x x x PSEL6 x x x PSEL5 x x x PSEL4 x x x PSEL3 x x x PSEL2 x x PSEL9 PSEL1 x x PSEL8 PSEL0 x x PSEL7 PMEN Res 0x0000 Micronas Feb. 10, 2005; 6251-579-1DS 239 CDC 32xxG-C DATA SHEET Table 33-21: Port interrupts (base addr. 0xF90000) Mnemonic Register Name Offs. 7 IRPM0 Interrupt Port Mode Register 0 0x02A 6 Register Configuration 5 4 3 2 1 0 13. 0 Res Section r/w 0 PIT3 0 0 PIT2 0 0 PIT1 0 0 PIT0 IRPM1 Interrupt Port Mode Register 1 0x02B r/w x x x x x x x x 0 PIT5 0 0 PIT4 0 Res Table 33-22: Power-saving module (base addr. 0xF90500) Mnemonic Register Name Offs. 7 WUS Wake-Up Source Register 0x050 6 Register Configuration 5 4 3 2 1 0 7.2. Section r/w r/w RTC WP7 x WP6 x WP5 x WP4 x WP3 x WP2 WP9 WP1 WP8 WP0 1 0 Res No HW reset SSR Sub Second Reload Register 0x054 r/w r/w r/w r/w x x x x x x x x x x x x 3 2 1 0 Res Bit 19 to 16 Bit 15 to 8 Bit 7 to 0 No HW reset SSC Sub Second Counter 0x058 r r r r x x x x x x x x x x x x 3 2 1 0 Res Bit 19 to 16 Bit 15 to 8 Bit 7 to 0 No HW reset RTC Real Time Counter 0x05C r/w r/w r/w r/w x x x x x x x x x x x x x HR MIN SEC x x 3 2 1 0 Res No HW reset 240 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Table 33-22: Power-saving module (base addr. 0xF90500) Mnemonic Register Name Offs. 7 WPM0 WPM2 WPM4 WPM6 WPM8 WSC Wake Source Control Wake Port Mode Register 0x060 0x061 0x062 0x063 0x064 0x068 r/w x x x x x AST RTC P 0 Res Register Configuration 6 5 4 3 2 1 0 Section r/w x MOD1 x No HW reset MOD0 0 Res 7.2. 0x00 after UVDD power-up OSC Oscillator Source Register 0x070 r/w RC 1 XK x XM 1 x LD x No HW reset SRC 0 Res RTCC RTC Control Register 0x074 r/w x x x No HW reset SEL 0 Res POL Polling Register 0x078 r/w r/w x ENA OE CLK x x DEL 0x00 PER 1 0 Res SMX Signal Multiplexer Register 0x07C r/w BYP x x x 0x00 x MUX 0 Res Table 33-23: Pulse frequency modulator (base addr. 0xF90100) Mnemonic Register Name Offs. 7 PFM0 PFM1 Pulse Width and Period Length Register 0x050 0x054 6 Register Configuration 5 4 3 2 1 0 18.2. Section w w w w INV x x x x x x x 3 2 1 0 Res Pulse Width Period Length (High Byte) Period Length (Low Byte) 0x00 Micronas Feb. 10, 2005; 6251-579-1DS 241 CDC 32xxG-C DATA SHEET Table 33-24: Pulse width modulator (base addr. 0xF90100) Mnemonic Register Name Offs. 7 PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 PWM8 PWM9 PWM10 PWM11 PWMC PWM Control Register PWM Register 0x040 0x041 0x042 0x043 0x044 0x045 0x046 0x047 0x048 0x049 0x04A 0x04B 0x04F w x x x x P1611 0 P169 0 P167 0 P165 0 P163 0 P161 0 Res Register Configuration 6 5 4 3 2 1 0 Section w 0 0 0 Pulse width value 0 0 0 0 0 Res 17.2. Table 33-25: Serial synchronous peripheral interfaces (base addr. 0xF90000) Mnemonic Register Name Offs. 7 SPI0D SPI1D SPI0M SPI1M SPI Mode Register SPI Data Register 0x010 0x012 0x011 0x013 6 Register Configuration 5 4 3 2 1 0 24.2. 0 0 0 Res Section r/w 0 0 0 Bit 7 to 0 of Rx/Tx Data 0 0 r/w BIT8 0 LEN9 0 RXSEL INTERN 0 0 0 SCLK 0 0 CSF 0 Res 242 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Table 33-26: Stepper motor VDO (base addr. 0xF90000) Mnemonic Register Name Offs. 7 SMVC Stepper Motor VDO, Control Register 0x05A 6 Register Configuration 5 4 3 2 1 0 20.2. 0 Res Section w x x x x 0 SEL 0 0 x x 0 QUAD SMVSIN Stepper Motor VDO, Sine Register 0x05B r w x x x x x x x BUSY 8bit Sine Value 0 0 0 0 0 0 0 0 Res SMVCOS Stepper Motor VDO, Cosine Register 0x05C w 0 0 0 8bit Cosine Value 0 0 0 0 0 Res SMVCMP Stepper Motor VDO, Back-Up Comparator Register Stepper Motor VDO, Multiplexer Register 0x05D r/w x x ACRF 0 ACRD 0 ACRB 0 ACRG 0 ACRE 0 ACRC 0 ACRA 0 Res SMVMUX 0x05E r/w r/w E B x C x D F 0x0000 A G 1 0 Res Table 33-27: Test registers (base addr. 0xF90000) Mnemonic Register Name Offs. 7 TSTAD2 TSTAD3 TST5 TST4 TST3 TST1 TST2 Test Register AD2 Test Register AD3 Test Register 5 Test Register 4 Test Register 3 Test Register 1 Test Register 2 0x0F8 0x0F9 0x0FB 0x0FC 0x0FD 0x0FE 0x0FF 6 Register Configuration 5 4 3 2 1 0 6.6. 0 0 0 Res Section w 0 0 0 For testing purposes only 0 0 Micronas Feb. 10, 2005; 6251-579-1DS 243 CDC 32xxG-C DATA SHEET Table 33-28: Timer (base addr. 0xF90000) Mnemonic Register Name Offs 7 TIM0L Timer 0 low byte 0x04E 6 Register Configuration 5 4 3 2 1 0 16. Section r w 1 Read low byte of down-counter and latch high byte Write low byte of reload value and reload down-counter 1 1 1 1 1 1 1 Res TIM0H Timer 0 high byte 0x04F r w 1 1 Latched high byte of down-counter High byte of reload value 1 1 1 1 1 1 Res TIM1 TIM2 TIM3 TIM4 Timer 1 Register Timer 2 Register Timer 3 Register Timer 4 Register 0x054 0x055 0x056 0x057 w 0 0 0 Reload value 0 0 0 0 0 Res 244 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Table 33-29: Universal asynchronous receiver transmitters (Base addr. 0xF90000) Mnemonic Register Name Offs. 7 UA0D UA1D UART Data Register 0x0A0 0x018 6 Register Configuration 5 4 3 2 1 0 25.3. Section r w x x x Receive register Transmit register x x x x x Res UA0C UA1C UART Control and Status Register 0x0A1 0x019 r RBUSY 0 w x x BRKD x x x FRER x x x OVRR 0 x x PAER x STPB 0 EMPTY 1 ODD 0 FULL 0 PAR 0 TBUSY 0 LEN 0 Res Res UA0BR0 UA1BR0 UA0BR1 UA1BR1 UA0IM UA1IM UA0CA UA1CA UA0IF UA1IF UART Baud Rate Register Low Byte 0x0A2 0x01A w 0 0 0 Bit 7 to 0 of Baud Rate 0 0 0 0 0 Res UART Baud Rate Register High Byte 0x0A3 0x01B w x - x - x 0 Bit 12 to 8 of Baud Rate 0 0 0 0 Res UART Interrupt Mask Register 0x0A4 0x01C w x - x - x - x - x - ADR 0 BRK 0 RCVD 0 Res UART Compare Address Register 0x0A5 0x01D w 0 0 0 Bit 7 to 0 of address 0 0 0 0 0 Res UART Interrupt Flag Register 0x0A6 0x01E r Test - Test - Test - Test - Test - ADR x BRK 0 RCVD 0 Res Micronas Feb. 10, 2005; 6251-579-1DS 245 CDC 32xxG-C DATA SHEET Table 33-30: Universal ports (base addr. 0xF90400) Mnemonic Register Name Offs. 7 U0D U1D U2D U3D U4D U5D U6D U7D U8D U0TRI U1TRI U2TRI U3TRI U4TRI U5TRI U6TRI U7TRI U8TRI U0NS U1NS U2NS U3NS U4NS U5NS U6NS U7NS U8NS Universal Port Normal-Special/Segment 2 Register Universal Port Tristate/Segment 1 Register Universal Port Data/ Segment 0 Register 0x000 0x010 0x020 0x030 0x040 0x050 0x060 0x070 0x080 0x001 0x011 0x021 0x031 0x041 0x051 0x061 0x071 0x081 0x002 0x012 0x022 0x032 0x042 0x052 0x062 0x072 0x082 r/w r/w S7 SG7_2 0 S6 SG6_2 0 S5 SG5_2 0 S4 SG4_2 0 S3 SG3_2 0 S2 SG2_2 0 S1 SG1_2 0 S0 SG0_2 0 Port LCD Res r/w r/w T7 SG7_1 1 T6 SG6_1 1 T5 SG5_1 1 T4 SG4_1 1 T3 SG3_1 1 T2 SG2_1 1 T1 SG1_1 1 T0 SG0_1 1 Port LCD Res Register Configuration 6 5 4 3 2 1 0 Section r/w r/w D7 SG7_0 0 D6 SG6_0 0 D5 SG5_0 0 D4 SG4_0 0 D3 SG3_0 0 D2 SG2_0 0 D1 SG1_0 0 D0 SG0_0 0 Port LCD Res 14.3. 246 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Table 33-30: Universal ports (base addr. 0xF90400) Mnemonic Register Name Offs. 7 U0DPM U1DPM U2DPM U3DPM U4DPM U5DPM U6DPM U7DPM U8DPM U0SLOW U1SLOW U2SLOW U3SLOW U4SLOW U5SLOW U6SLOW U7SLOW U8SLOW U0LVL U1LVL U2LVL U3LVL U4LVL U5LVL U6LVL U7LVL U8LVL Universal Port Level Register Universal Port Slow Mode Register Universal Port Double Pull-Down Mode/ Segment 3 Register 0x003 0x013 0x023 0x033 0x043 0x053 0x063 0x073 0x083 0x004 0x014 0x024 0x034 0x044 0x054 0x064 0x074 0x084 0x005 0x015 0x025 0x035 0x045 0x055 0x065 0x075 0x085 r/w A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 Res r/w S7 0 S6 0 S5 0 S4 0 S3 0 S2 0 S1 0 S0 0 Res Register Configuration 6 5 4 3 2 1 0 Section r/w r/w D7 SG7_3 0 D6 SG6_3 0 D5 SG5_3 0 D4 SG4_3 0 D3 SG3_3 0 D2 SG2_3 0 D1 SG1_3 0 D0 SG0_3 0 Port LCD Res 14.3. Micronas Feb. 10, 2005; 6251-579-1DS 247 CDC 32xxG-C Table 33-30: Universal ports (base addr. 0xF90400) Mnemonic Register Name Offs. 7 U0PIN U1PIN U2PIN U3PIN U4PIN U5PIN U6PIN U7PIN U8PIN U0MODE U1MODE U2MODE U3MODE U4MODE U5MODE U6MODE U7MODE U8MODE Universal Port Mode Register Universal Port Pin Register 0x006 0x016 0x026 0x036 0x046 0x056 0x066 0x076 0x086 0x007 0x017 0x027 0x037 0x047 0x057 0x067 0x077 0x087 r/w L7 0 L6 0 L5 0 L4 0 L3 0 L2 0 L1 0 L0 0 Res DATA SHEET Register Configuration 6 5 4 3 2 1 0 Section r P7 x P6 x P5 x P4 x P3 x P2 x P1 x P0 x Res 14.3. 248 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 34. Control Register and Memory Interface 34.1. Control Register CR When exiting Reset, the device will start up in a configuration defined by the CR setting. For details on how to set the CR see chapter "Core Logic". A full description of the functionality of all CR bits is given below. Among others, the CR allows to configure the memory interface for connection to a variety of external memories. TFT TETM EB1 r/w1: Trace Bus Full Trace (Emu parts only, Table 34-3) Trace Bus ETM (Emu parts only, Table 34-3) External Bus Flag 1 (Emu/MCM parts only, Table 34-1) Power-saving mode of memory interface. Emu Bus configured for external Flash memory. Pin signals FBUSQ, BWQ0 to 3 and CE1Q are disabled and pulled low weakly. In CPU SLOW mode pin signal CE0Q activates flash memory only for 1/128th of access cycle. Emu Bus configured for standard external Memory. CE0Q and CE1Q always enable memory for full access cycles. Emu Bus Width (Emu/MCM parts only, Tables 34-1, 34-2) Emu Bus configured for 16-bit-wide external memory. For illustration see Fig. 34-13. Bits CR.PSA, CR.STPCLK and CR.RESLNG are set to one and bit CR.TSTTOG is set to zero. Emu Bus configured for 32-bit-wide external memory. Emu Bus in Asynchronous Mode (Table 34-1) (Emu/MCM parts only) Emu Bus configured for asynchronous external memory. Emu Bus configured for synchronous external memory. In synchronous mode the address bus (A) and chip enable (CExQ) latches are transparent. Multifunction pin Mode (Tables 34-9) Application JTAG Interface Enabled if TEST2 pin is high (Fig. 34-1) Disabled CR 7 r/w x Control Register 6 x 5 x x TETM MAP 4 x x EB1 3 x x EBW IBOOT 2 x TSTTOG EASY IROM 1 x EWE 0 x PSA 3 2 1 0 Offs r/w STPCLK RESLNG r/w r/w EB2 JTAG TFT ENDIAN r/w0: MFM IRAM ICPU EBW r/w1: Value of memory location 0x20 to 0x23 Res The upper half word of register CR is loaded from location 0x22/0x23 only if flag EBW is at zero. If EBW is at one, the upper half word is initialized to 0xFFFB. STPCLK Stop Clock (Emu parts only) r/w1: Peripheral clocks are stopped in debug mode. r/w0: Peripheral clocks are always active. Timers are stopped with a resolution of 1/f0. RESLNG Reset Pulse Length r/w1: Pulse length is 8/FXTAL r/w0: Pulse length is 2048/FXTAL This bit specifies the length of the reset pulse which is output at pin RESETQ following an internal reset. If pin TEST is 1 the first reset after power on is short. The following resets are as programmed by RESLNG. If pin TEST is 0 all resets are long. TSTTOG TEST2 Pin Toggle (Table 34-9) This bit is used for test purposes only. If TSTTOG is true in IC active mode, pin TEST2 can toggle the multifunction pins between bus mode and normal mode. EWE Emu Bus Write Enable r/w1: Enabled (No data security). r/w0: Disabled. This flag has to be set to allow Emu bus writes or Flash programming (MCM). For details please refer to section "Device Lock Module (DLM)". PSA Program Storage Access r/w1: 16-bit access. r/w0: 32-bit access. This bit allows, in EMU parts, to set the data bus access width to ROM and Flash program storage (Table 34-2). EB2 r/w1: r/w0: External Bus Flag 2 (Table 34-1) CE0Q and CE1Q select two external chips. OEQ and WEQ select one external chip connected to CE0Q (do not use CE1Q). For illustration see Fig. 34-13. r/w0: EASY r/w1: r/w0: MFM JTAG r/w1: r/w0 ENDIAN Endian setting ARM Core r/w1: Little endian. r/w0: Big endian. Don't change this flag dynamically MAP IBOOT IROM IRAM ICPU r/w1: r/w0: Mapping (Table 34-4) Internal Special Function ROM (Tables 34-5, 34-8) Internal ROM (Table 34-6) Internal RAM (Tables 34-7, 34-8) Internal CPU Enable internal CPU. Disable internal CPU Micronas Feb. 10, 2005; 6251-579-1DS 249 CDC 32xxG-C Table 34-3: TETM and TFT usage Appl. JTAG interface & nTRST Emu only 1 Emu. JTAG interface DATA SHEET TEST2 TFT CR.JTAG TETM Trace Bus Mode Disabled (Gnd) (Except for DBGACK, nRESET, FSYS) Analyzer ETM ETM D0 to D31 active ETM 1 1 for external memory access only Off Fig. 34-1: Enabling JTAG interfaces 0 1 0 1 0 0 always for external memory access only always Off On On Table 34-1: Emu bus configuration for some commonly used external memories External Memory Type EASY EBW EB2 EB1 Program Memory (CE0Q) Data or Special Function Memory (CE1Q) Table 34-4: MAP usage MAP 1 0 0 1 0 0 1 x mirrors RAM base offset 0xC0.0000 to 0 maps ROM/Flash base offset 0x20.0000 to 0 mirrors special-function ROM base offset 0xF0.0000 to 0 Mapping Effect 1 0 0 1 0 0 0 1 32-Bit sync SRAM (e.g. MT55L256L32F) 32-Bit async Flash (e.g. 2 x Am29F400BT or Am29LV400BT) 16-Bit async. Flash (e.g. Am29F400BT or Am29LV400BT) don't use Table 34-5: IBOOT usage IBOOT MFM 1 0 x 0 x 0 1 x disable specialfunction ROM ext. via Emu bus selected Special Function ROM source QFP128 Emu 0 1 1 1 0 external via multifunction pins in bus mode Table 34-2: Control of Emu bus timing by PSA and EBW EBW PSA Bus Width Number of cycles for 32-bit access 1 cycle 1 1 x internal special-function ROM 0 0 1 1 0 1 0 1 32 Bit Don't use 32 Bit 16 Bit Table 34-6: IROM usage IROM selected ROM/Flash source QFP128 Emu 2 cycles 0 1 external via multifunction pins in bus mode internal ROM/Flash external via Emu bus 250 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Table 34-7: IRAM usage IRAM MFM 1 0 x 1 1 x 0 x 0 1 x disable RAM internal RAM ext. via Emu bus selected RAM source QFP128 Emu 0 external via multifunction pins in Bus mode Table 34-8: CE1Q Selections IBOOT x 0 1 IRAM CE1Q selects 0 1 1 external RAM external special-function ROM No external access Table 34-9: TSTTOG and MFM usage in ROM/Flash parts TSTTOG MFM 1 0 TEST2 Pin x 0 1 0 1 0 1 x 0 1 1 0 0 1 x 0 1 1 1 x x Multifunction Pins 0 0 0 1 Bus mode 0 Bus mode 0 Port mode Bus mode 1 Bus mode 1 Port mode Bus mode 2 Bus mode 2 Port mode Port mode Micronas Feb. 10, 2005; 6251-579-1DS 251 CDC 32xxG-C DATA SHEET ICPU CPU IRAM predecram RAM IROM predecrom & ROM IBOOT predecboot & SFR & Data Bus Ports 1 & 0 Mux 1 Test Bus MFM0 MFM1 FBUS IRAM predecram IROM predecrom IBOOT predecboot predecio & & 1 & MFM0 MFM1 TESTTOG TEST2 Pin MFPL external access 1 & & & 1 EMUTRI Addr. & Ctrl. Mem Ifc TFT MFM0 MFM1 EMUTRI FBUS Data MDDL & Data Mem Ifc & MCDL EMUTRI FBUSQ TETM ETM TFT Emu only Analyzer & 0 Mux 1 Trace Bus Fig. 34-2: Bus interfaces 34.2. Memory Clock Delay Lines The memory clock delay lines allow access optimization to external synchronous memory. Only EMU parts need these registers to be configured. MDDL and MCDL must only be modified in FAST mode, and only by increments of one by one. MDL 7 w w x x Memory Delay 6 x x 5 x x 4 x x 0x0000 3 2 MDDL MCDL 1 0 1 0 Offs Res MDDL w0 to 15: MCDL w0 to 15: Memory Data Delay Delay of data driven to memory port from 0 to 15 ns in 1 ns steps. Memory Clock Delay Delay of clock FBUSQ for external memory from 0 to 15 ns in 1 ns steps. 252 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 34.3. External Memory Interface 34.3.1. Interfacing examples EVDD = 5 V is required for the following interfacing examples. 5V CE0Q OEQ WEQ/RWQ CE# OE# WE# RESET# BYTE# RY/BY# Flash-EEPROM 256k x 16 A[18:8], AICU[7:2], AMCS1 D[15:0] A[17:0] DQ[15:0] GND Fig. 34-3: Asynchronous Flash EEPROM (e.g. Am29F400B) as program memory BWQ0 BWQ1 BWQ2 BWQ3 CExQ OEQ CE# asyn. SRAM 512k x 8 WE# OE# A[18:0] I/O[7:0] A[20:8], AICU[7:2] D[31:0] D[31:24] D[23:16] D[15:8] D[7:0] CE# asyn. SRAM 512k x 8 WE# OE# A[18:0] I/O[7:0] CE# asyn. SRAM 512k x 8 WE# OE# A[18:0] I/O[7:0] CE# asyn. SRAM 512k x 8 GND WE# OE# A[18:0] I/O[7:0] 5V Fig. 34-4: Asynchronous SRAM (e.g. KM684002B) as emulation program memory 3V3 FBUSQ 5V to 3V3 Level Shifter CE0Q WEQ/RWQ BWQ[3:0] CLK CE# R/W# BW#[d:a] SSRAM 256k x 32 SA, SA1,SA0 DQ[d:a] CKE MODE ZZ CE2 CE2# OE# ADV/LD# GND A[19:8], AICU[7:2] D[31:0] Fig. 34-5: Synchronous SRAM (e.g. MT55L256L32F) as emulation program memory Micronas Feb. 10, 2005; 6251-579-1DS 253 CDC 32xxG-C DATA SHEET 3V3 FBUSQ 5V to 3V3 Level Shifter CE1Q WEQ/RWQ BWQ[3:0] CLK CE# R/W# BW#[d:a] SSRAM 256k x 32 SA, SA1,SA0 DQ[d:a] CKE MODE ZZ CE2 CE2# OE# ADV/LD# GND A[19:8], AICU[7:2] D[31:0] Fig. 34-6: Synchronous SRAM (e.g. MT55L256L32F) as emulation RAM or special-function memory 34.3.2. External Trace Interfacing For a mapping of the IC pins to external trace tools see the "Specification of the Evaluation Board Kit (EVB)". 34.3.3. Memory Interface Characteristics Table 34-10: UVSS = UVSS1 = FVSS = HVSSn = EVSSn = AVSS = 0 V, 3.5 V < AVDD = UVDD = UVDD1 < 5.5 V, 4.5 V < EVDDn < 5.5 V, TCASE = 0C to 35C, CL = 70 pF Symbol DFBUSQ Parameter FBUSQ High to Low Ratio Min. 47.5 Typ. Max. 52.5 Unit % Test Conditions PLL mode Synchronous SRAM tsAS tsAH tsCES tsDSR tsDHR tsDSW tsDDT sync Address Setup Time sync Address Hold Time sync Chip Enable Setup sync Data Setup Read Time sync Data Hold Read Time sync Data Setup Write Time sync Data Drive Tristate 0 0 0 18.5 0 0 0 12.5 ns ns 12.5 ns ns ns 10 ns ns Asynchronous SRAM taAS taAH taCES taOES taBWS taDSR taDHR async Address Setup Time async Address Hold Time async Chip Enable Setup async Output Enable Setup async Byte Write Setup async Data Setup Read async Data Hold Read Time 0 0 0 0 0 18.5 0 2.5 ns ns FSYS<40MHz 2.5 ns ns ns ns ns FSYS<40MHz 254 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C Table 34-10: UVSS = UVSS1 = FVSS = HVSSn = EVSSn = AVSS = 0 V, 3.5 V < AVDD = UVDD = UVDD1 < 5.5 V, 4.5 V < EVDDn < 5.5 V, TCASE = 0C to 35C, CL = 70 pF Symbol taDSW taDDT Parameter async Data Setup Write async Data Drive Tristate Min. 0 Typ. Max. 10 Unit ns ns Test Conditions 0 Table 34-11: UVSS = UVSS1 = FVSS = HVSSn = EVSSn = AVSS = 0 V, 3.5 V < AVDD = UVDD = UVDD1 < 5.5 V, 4.5 V < EVDDn < 5.5 V, TCASE = -40C to 85C, CL = 70 pF Symbol DFBUSQ Parameter FBUSQ High to Low Ratio Min. 47.5 Typ. Max. 52.5 Unit % Test Conditions PLL mode Synchronous SRAM tsAS tsAH tsCES tsDSR tsDHR tsDSW tsDDT sync Address Setup Time sync Address Hold Time sync Chip Enable Setup sync Data Setup Read Time sync Data Hold Read Time sync Data Setup Write Time sync Data Drive Tristate 0 0 0 20.5 0 0 0 12.5 ns ns 12.5 ns ns ns 10 ns ns Asynchronous SRAM taAS taAH taCES taOES taBWS taDSR taDHR taDSW taDDT async Address Setup Time async Address Hold Time async Chip Enable Setup async Output Enable Setup async Byte Write Setup async Data Setup Read async Data Hold Read Time async Data Setup Write async Data Drive Tristate 0 0 0 0 0 20.5 0 0 0 2.5 ns ns FSYS<40 MHz 2.5 ns ns ns ns ns FSYS<40 MHz 10 ns ns Table 34-12: UVSS = UVSS1 = FVSS = HVSSn = EVSSn = AVSS = 0 V, 3.5 V < AVDD = UVDD = UVDD1 < 5.5 V, 3 V < EVDDn = FVDD < 3.6 V, TCASE = -40C to 85C, CL = 10 pF Symbol Parameter Min. Typ. Max. Unit Test Conditions Asynchronous Flash taAS taAH taCES taOES taBWS async Address Setup Time async Address Hold Time async Chip Enable Setup async Output Enable Setup async Byte Write Setup 0 0 0 0 0 2.5 ns ns FSYS<40MHz 2.5 ns ns ns FSYS<40MHz Micronas Feb. 10, 2005; 6251-579-1DS 255 CDC 32xxG-C DATA SHEET Table 34-12: UVSS = UVSS1 = FVSS = HVSSn = EVSSn = AVSS = 0 V, 3.5 V < AVDD = UVDD = UVDD1 < 5.5 V, 3 V < EVDDn = FVDD < 3.6 V, TCASE = -40C to 85C, CL = 10 pF Symbol taDSR taDHR taDSW taDDT Parameter async Data Setup Read async Data Hold Read Time async Data Setup Write async Data Drive Tristate Min. 18.5 Typ. Max. Unit ns Test Conditions 0 0 0 10 ns ns ns FSYS nWAIT FBUSQ tsAS A A1 A2 tsCES CExQ tsAS WEQ/RWQ tsAS BWQ[3:0] D[31:0] 6) read data D1 6) read data tsDSR D2 tsDHR 6) write data tsDSW D3 tsDDT 6) tsAH tsAH A3 tsAH tsAH Fig. 34-7: Sync SRAM timing, 0 wait states 256 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C FSYS nWAIT FBUSQ tsAS A A1 tsCES CExQ A2 tsAH tsAH WEQ/RWQ BWQ[3:0] D[31:0] tsDSR D1 6) read data, 1 wait state D2 6) write data tsDHR 6) read data, no wait state Fig. 34-8: Sync SRAM timing, read with wait state, followed by a write cycle FSYS nWAIT FBUSQ tsAS A A1 tsCES CExQ tsAS WEQ/RWQ tsAS BWQ[3:0] D[31:0] 6) write data, no wait state D1 6) tsDSW D2 write data, 1 wait state tsDDT 6) read data tsAH tsAH A2 tsAH tsAH Fig. 34-9: Sync SRAM timing, write with wait state, followed by a read cycle Micronas Feb. 10, 2005; 6251-579-1DS 257 CDC 32xxG-C DATA SHEET FSYS nWAIT FBUSQ taCES CExQ taAS A A1 A2 A3 taOES OEQ taBWS BWQ[3:0], WEQ/RWQ D[31:0] 6) write data D1 6) read data D2 6) read data taDSR D3 taDHR 6) write data taDSW D4 taDDT 6) taAH taAH taAH A4 taAH Fig. 34-10: Async SRAM/Flash timing, 0 wait states FSYS nWAIT FBUSQ taCES CExQ taAS A A1 taOES OEQ A2 taAH taAH taAH BWQ[3:0], WEQ/RWQ D[31:0] taDSR D1 6) read data, 1 wait state D2 6) write data taDHR 6) read data, no wait state Fig. 34-11: Async SRAM/Flash timing, read with wait state, followed by a write cycle 258 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C FSYS nWAIT FBUSQ taCES CExQ taAS A A1 A2 taAH taAH OEQ taBWS BWQ[3:0], WEQ/RWQ D[31:0] D1 6) write data, no wait state 6) taDSW D2 write data, 1 wait state taDDT 6) read data taAH Fig. 34-12: Async SRAM/Flash timing, write with wait state, followed by a read cycle 6) During the high level of FBUSQ the previous data bus levels are weakly held. Thus the data bus is defined when the bus drivers are tristate and FBUSQ is high. See section `Electrical Characteristics' for the weak hold currents for pull-down (Ipd) and for pull-up (Ipu). fast mode FSYSint FBUSQint CE0Q WEQ/RWQ OEQ slow mode Fig. 34-13: CE0Q timing in PLL/FAST and SLOW/DEEP SLOW modes (CR.EB2 set to 0, CR.EB1 and CR.EASY set to 1) CE0Q is used for low power mode. Input data are latched with the rising edge of CE0Q and are weakly held as long as CE0Q stays high. Micronas Feb. 10, 2005; 6251-579-1DS 259 CDC 32xxG-C DATA SHEET 260 Feb. 10, 2005; 6251-579-1DS Micronas DATA SHEET CDC 32xxG-C 35. Differences This chapter describes differences between this document and the predecessor document "CDC32xxG-C Automotive Controller Family Hardware Manual, CDC3205G-C Automotive Controller Specification" (6251-579-1PD). Section Introduction Pins Electrical Characteristics Description Table 1-1 changed. Figure 2-3 changed. Characteristics: Changed value: UIDDi, UIDDp, UIDDpe, UIDDf, tsoci, thoci, tsoce, thoce, tsi, thi, tbtj, tfed Deleted parameters: tsrx, tdtx New parameters: tIOd, tso, tho Figure 3-3: deleted. CPU and Clock System Figure 4-2 modified. Section 4.7.3.1 corrected. Memory and SFR Core Logic Figure 5-1 corrected. Figure 6-1 corrected. Section 6.5.5 clarified. ICU AVDD Analog Section Stepper Motor Module UART I2 C Features extended. Section 15.7 clarified. Section 20. re-ordered. Figure 25-1 changed. Figure 26-1 changed. Section 26.2 clarified. CAN Control Register and Memory Interface Section 27.2.3 clarified. Section 34.1. clarified. Table 34-1 simplified. Table 34-10, changed values: tsAS, tsCES, tsDSR, tsDSW, tsDDT, taAS, taCES, taDSR, taDSW, taDDT Table 34-11, added parameters: DFBUSQ, tsAH, tsCES, tsDSR, tsDHR, tsDSW, tsDDT, taAS, taAH, taCES, taOES, taBWS, taDSR, taDHR, taDSW, taDDT Table 34-12 added. Micronas Feb. 10, 2005; 6251-579-1DS 261 CDC 32xxG-C 36. Data Sheet History 1. Advance Information: "CDC32xxG-C V1.0 Automotive Controller - Family User Manual, CDC3205G-C Automotive Controller Specification", Feb. 21, 2002, 6251-579-1AI. First release of the advance information. Originally created for HW versions CDC3205G-C1 and CDC3207G-C1. 2. Advance Information: "CDC32xxG-C V2.0 Automotive Controller - Family User Manual, CDC 3205G-C Automotive Controller Specification", June 6, 2002, 6251-579-2AI. Second release of the advance information. Originally created for HW versions CDC3205G-C2 and CDC3207G-C2. 3. Preliminary Data Sheet: "CDC32xxG-C Automotive Controller - Family User Manual, CDC 3205G-C Automotive Controller Specification", June 12, 2003, 6251-579-1PD. First release of the preliminary data sheet. Originally created for HW version CDC3205G-C2. 4. Data Sheet: "CDC 32XXG-C Automotive Controller - Family User Manual, CDC 3205G-C Automotive Controller Specification", Feb. 10, 2005, 6251-579-1DS. First release of the data sheet. Originally created for HW version CDC3205G-C2. DATA SHEET Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-579-1DS All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH. 262 Feb. 10, 2005; 6251-579-1DS Micronas |
Price & Availability of CDC3257G-C2
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |